Using a component in loop

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mahmood.n

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I want to instantiate (port map) a component within a process but it seems that it is not allowed. Simply, the component
gets two integers and sends two outputs and I want to feed array elements to that.

Code: 
for i in 0 to 7 loop
	u1: myComponent port map( a(i), a(i+1), a(i), a(i+1));
end loop;


How to fix that?
 

Instantiate the component outside of a process.
Instatiating a component in a process makes no sense, as that would be like adding a removing chips from a circuit board while it is running.
 

So how can I pass (map) array elements to the component?
 

You can instantiate the component in a generate loop.
 

I wrote

Code: 
architecture behav of switch is
	component cross port( x, y: in integer range 0 to 31;
		 				s, b: out integer range 0 to 31); 
	end component;												
	signal tmp1, tmp2: int_array;
begin	 	 					 
	tmp1 <= ip;
	gen_var:
	for i in 0 to 6 generate
		u1: cross port map( tmp1(i), tmp1(i+1), tmp2(i), tmp2(i+1) );
	end generate gen_var;
	ot <= tmp2;
end;

I have to say that int_array is an array of integer which is defined as

Code: 
type int_array is array (0 to 7) of integer range 0 to 31;

But I get this error Signal "s" has multiple sources but is not resolved. How can I fix that?
 

The error is expectable because the elements of tmp2 are connected to both outputs s and b. Don't know if it's a typo or an error of reasoning.

Better to use named association for ports to avoid confusion.
 

OK I think I can fix that. I will come back.

Code: 
                +-------+
     tmp1(0) ---|       |---- tmp2(0)
     tmp1(1) ---|       |---- tmp2(1)
        ...
     tmp1(7) ---|       |---- tmp2(7)
                +-------+
 

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