Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

User defined primitives in verilog

Status
Not open for further replies.

ashwini jayaraman

Member level 2
Joined
Jan 17, 2013
Messages
49
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,601
I tried simulating the following code in modelsim.

//instantiate primitive
//verilog model:circuit instantiation of circuit_UDP_1

module circuit_with_UDP_1(F,A,B,C,D);
output F;
input A,B,C,D;
UDP_1 (F,A,B,C,D);
endmodule


primitive UDP_1(f,a,b,c,d);
output f;
input a,b,c,d;
//truth table for f=F(a,b,c,d)=summation(7,11,13,14,15)
table
// a b c d : f
0 0 0 0 : 0;
0 0 0 1 : 0;
0 0 1 0 : 0;
0 0 1 1 : 0;
0 1 0 0 : 0;
0 1 0 1 : 0;
0 1 1 0 : 0;
0 1 1 1 : 1;
1 0 0 0 : 0;
1 0 0 1 : 0;
1 0 1 0 : 0;
1 0 1 1 : 1;
1 1 0 0 : 0;
1 1 0 1 : 1;
1 1 1 0 : 1;
1 1 1 1 : 1;
endtable
endprimitive

But I cannot simulate it when I made a right-click on it, my simulate option is disabled and it has 'U' symbol on its left rather than the 'M'.Can anyone tell me, what is the actual bug in this program???If my simulation procedure is wrong, could you please let me know the correct procedure?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top