user constraint file in vivado

[preethi19]

hi all i am in my beginner stage with vhdl programming. I built a BASK modulator using vhdl lang in vivado. I know how to compile a source code and then write the test bench and simulate the output waveform. From there on out i don't know what to do. I need to implement it on an FPGA. There was something about ucf file and pin location which i have no clue about.. I have no idea on how to write an ucf file. Can anyone pls help me with the steps or can anyone pls provide me some links that has all the steps so that i can carry on from the simulation part.. thank you!!!

 

[aruipksni]

hi all i am in my beginner stage with vhdl programming. I built a BASK modulator using vhdl lang in vivado. I know how to compile a source code and then write the test bench and simulate the output waveform. From there on out i don't know what to do. I need to implement it on an FPGA. There was something about ucf file and pin location which i have no clue about.. I have no idea on how to write an ucf file. Can anyone pls help me with the steps or can anyone pls provide me some links that has all the steps so that i can carry on from the simulation part.. thank you!!!

in vivado you need to generate XDC file.
you can graphically generate your pins constraints from the i/o planining layout.

 

[aminpix]

after compiling and analyzing the code a window will pop up and there you must click on "Open implementation design" it may directly bring you to the I/O planing. If not, at the bottom of the page click on the "I/O ports" tag and assign pins there. After assigning I/O pins I usually again synthesize the code and this time, after synthesizing and compiling, i select "generate bit stream".
finally when bit stream generates, open hardware manager and program the code.
It is better to connect your programmer before running the Vivado. sometimes it can not recognize.