use of verilog to develop behavioural model for a comparator

[funjoke]

comparator

use verilog to develop a behavioural model for a comparator that has following requirement:

-The comparator compares two N-bit data
-The comparator is able to indicate "lesser than","greater than" and "equal to"relationship between the two N-bit data.
-All output must be registered the rising edge of the clock signal
-The comparator can be reset using an active-low asynchronous reset signal


This question i really dunno how to do at all.can anybody help me ?

 

[funjoke]

Re: comparator

Cac anybody give me any guidance or outline to do this question ?really need your help thanks