use of parameters in verilog

[arunssn]

what are the advantage of using parameters while coding, is there any complexity reduced

 

[echo47]

Verilog parameters are a convenience to make your life easier. They don't affect the synthesized results.

 

[jjww110]

easy to transplant to other system

 

[vivek]

helps u make your code more reuseable. changes can be made to the code most easily, makes it more readeable. Very useful in FSM coding.

 

[stay_in_chaos]

parametrs are just like enumerated data types in vhdl that are usr defined.
basically when you have ur own defined parameters then it's quite eassy to work on.

OK

 

[maks10]

complexity is reduced in the sense, when u need to change a value i.e used @ multpile places u need 2 change only once. Like # define in C. If Anyother advantages pls addon....

 

[EleApollo]

the advantage of using parameter :
1 reuse. using parameter can easily resue the design
2 maitain.

 

[visualart]

Is is readable and interpretative-self using the parameter. Othewise, the parameter may be redefinited when it is quoted, So it is convenient reuse.

 

[farmerwang]

Make your module configurable, easy to maitain, descriptive ...

 

[weng]

what is the difference between parameter and define?

 

[stevepre]

parameter is valid only within this module.
define ........ after defined, the value stays there and can propagate through all the codes that are compiled later on.

Use parameter is safer.
but sometimes, using `define is pretty convenient, but just be careful.

 

[Vonn]

don't you think using parameter - for FSM - for example will force the synthesis tool to encode your state control to the one you wrote in your parameter definition even if was not the optimum technique for FSM state encoding ?, i mean you just use parameter - usually in FSM - to make your code readable , I agree with that , but look to the other side .. what do you think

 

[xuanzhu]

increase the reusability and upgradability of your code

 

[funster]

using parameter can improve code's readability.

best regards

what are the advantage of using parameters while coding, is there any complexity reduced

 

[sree205]

Parameters can be used in FSMs compared to `define. Say, if states like idle, read, write are declared using `define and if the design contains multiple FSMs, it might be difficult to debug the design. Here parameters come in handy.

 

[tigerajs]

of course , you can change it very covinent