Use of 'inout' ports in Verilog

[dpaul81]

Hi all,

A digital unit has two buses both of them are 32bits wide (say bus1 & bus2) and can either Rx or Tx data, so I am declaring them as INOUT ports in Verilog.
There are also some signals, and according to their conditions data has to be moved from bus1 to bus2 or bus2 to bus bus1.

Can anyone tell me how to store the data from one bus in a register and then pass off the same to the next bus & vice-versa!
Should I declare some internal variables of type wire and then do the data transfer or should I have to declare an int. reg. and then do the shifting?

Actually I tried coping the data in both a wire & reg, but I am always getting the error "A net is not a legal lvalue in this context"!

Plz tell me the principle! A sample bit of code will also be very useful!

Thanks,
dpaul

 

[dincay]

You can use this piece of code I think.
data_dir determines which port is output and whick port is input. You can write data to bus1reg or bus2reg and read data from bus1 or bus2.
For example if bus1 and bus2 are connected to each other and if data_dir=1, then bus1 is output and bus2 is input. If you read bus2 at this time you will read bus1reg.

inout wire [31:0] bus1, bus2;
reg [31:0] bus1reg, bus2reg;
bus1 = data_dir ? bus1reg : 32'hZZZZ_ZZZZ;
bus2 = ~data_dir ? bus2reg : 32'hZZZZ_ZZZZ;

 

[dpaul81]

Hi....thanks for the reply!

I got my code working! But now I am facing a problem in the testbench!

Since I am having inout ports, so what corresponding mapping must I have in a testbench?
(For normal in or out port, Verilog says that in a testbench, these ports must be driven from a register. But what about inout ports???)

---------- Post added at 13:46 ---------- Previous post was at 13:38 ----------

To put it in another way............since I am having INOUT ports, so when I am simulating the testbench, the error is INOUT PORTS MUST BE CONNECTED TO NETS.

ok......I then declare these INOUT ports in my testbench as nets! But then how can I drive these INOUT ports in my testbench if they are not registers?

 

[dincay]

I am not sure but maybe the same thing can be used in testbenches too.