Use of Dynamic Clock Select on LatticeECP3

[LatticeSemiconductor]

Hi there,

This is related to the ECP3 FPGA from Lattice Semiconductor
I am experimenting with the DCS (dynamic clock select) functionality described in the LatticeECP3 Handbook. It's actually quite simple it just gets two clock signals and assigns one of it depending on the clock select signal (like a MUX2)

The code i used was pretty much a copy and paste from the handbook, and it simulates and compiles well, unless however, i comment that line in the code. Otherwise, it gives me a "formal dcsmode is not declared" and doesn't compile anymore. Can anyone help? (I'd like to uncomment that line)

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
entity dcs_top is
  port (
        CLK_SYS : in std_logic;
        CLK_DCS : in std_logic;
        RESET   : in std_logic;
        CLK_SEL : in std_logic;
        LED     : out std_logic 
  ) ;
end entity ; -- dcs_top
 
architecture beh_dcs of dcs_top is
 
    --   +----------------+----------------------------------------------+---------------+-------------+
    --   | Attribute Name |                  Description                 |      Output   | Value       |
    --   |                |                                              | SEL=0 | SEL=1 |             |
    --   +----------------+----------------------------------------------+-------+-------+-------------+
    --   |                | Rising edge triggered, latched state is high | CLK0  | CLK1  | POS         |
    --   |                | Falling edge triggered, latched state is low | CLK0  | CLK1  | NEG         |
    --   |                | Sel is active high, Disabled output is low   |   0   | CLK1  | HIGH_LOW    |
    --   |    DCS MODE    | Sel is active high, Disabled output is high  |   1   | CLK1  | HIGH_HIGH   |
    --   |                | Sel is active low, Disabled output is low    | CLK0  |   0   | LOW_LOW     |
    --   |                | Sel is active low, Disabled output is high   | CLK0  |   1   | LOW_HIGH    |
    --   |                | Buffer for CLK0                              | CLK0  | CLK0  | CLK0        |
    --   |                | Buffer for CLK1                              | CLK1  | CLK1  | CLK1        |
    --   +----------------+----------------------------------------------+-------+-------+-------------+
    COMPONENT DCS
        -- synthesis translate_off
        GENERIC (
            DCSMODE : string := "POS"
        );
        -- synthesis translate_on
        PORT (
            CLK0  :IN std_logic ; -- 30 MHz
            CLK1  :IN std_logic ; -- 80 MHz
            SEL   :IN std_logic ;
            DCSOUT:OUT std_logic
        ) ;
    END COMPONENT;
    
    attribute DCSMODE            : string;
    attribute DCSMODE of DCSinst0: label is "POS";
    signal dcsclk                : std_logic;
    signal sign                  : std_logic;
    signal cnt                   : integer range 0 to 33_000_000;
 
begin
 
        DCSInst0: DCS
--      GENERIC MAP (DCSMODE => "POS")
        PORT MAP (
            SEL    => CLK_SEL,
            CLK0   => CLK_DCS,
            CLK1   => CLK_SYS,
            DCSOUT => dcsclk
        );
        
        clk_div : process (dcsclk, RESET) 
        begin
            if RESET = '1' then
                cnt <= 0;
                sign <= '0';
            elsif rising_edge (dcsclk) then
                if cnt = 33_000_000 then
                cnt <= 0;
                sign <= not sign;
            else
                cnt <= cnt + 1;
                end if;
            end if;
        end process;
    
        LED <= sign;
 
end architecture ; -- beh_dcs

---

Did i made a mistake or need to include some library? Many thanks in advance