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Use of decoupling cap either from PMOS or NMOS

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hung_wai_ming@hotmail.com

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Anyone can give me some reasons, how we should choose PMOS or NMOS as decoupling capacitor on chip? Despite their different capacitance value / um
 

peterwang

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The main reason between PMOS and NMOS is the gate voltage.

If your gate voltage is low, you need to use PMOS decoupling cap, so as to maintain ON stage of PMOS cap.

Simiarly, you should use NMOS decoupling cap, when your gate voltage is high.
 

peterwang

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NMOS cap, where the gate is connected to your power supply.
 

hung_wai_ming@hotmail.com

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Hey,

Why not PMOS cap, with gate connected to ground as well?
I noticed from another topic ppl said PMOS is more well controllled.
 

rania_hassan

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both can be used but NMOS gives less channel resistance for the same aspect ratio so you can get smaller time constant
Note: De-couping caps are considered large current devices as they should supply current at the instance of switching, so a grad ring should surround the de-coupling cap to reduce the latchup
best regards,
Rania
 

quanble

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Hi, Rania
Why NMOS gives larger capacitance than PMOS for the same aspect ratio in the same process ?Both NMOS and PMOS capacitor are caculated by planer capacitor formula .They have same oxide thickness ,so the value is equal.

rania_hassan said:
both can be used but NMOS gives larger capacitance for the same aspect ratio
Note: De-couping caps are considered large current devices as they should supply current at the instance of switching, so a grad ring should surround the de-coupling cap to reduce the latchup
best regards,
Rania
 

rania_hassan

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Hi quanble,
Yes you are right, but still NMOS is preferred over PMOS as the parasitic channel resistance of NMOS is less than it for the PMOS which makes the time constant of NMOS is smaller that it for the PMOS & hence you can get better performance
Sorry for mixing it up .
best regards,
Rania

Added after 4 minutes:

Hi,
To get also smaller parasitic resistance for the decoupling cap, the length shouldn't be too small, which increase the gate resistance and also not to large
There is a perfect value for it dependent on the process used
best regards,
Rania
 

laststep

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Hope u all can correct me if i am wrong,
NMOS has larger value compare to PMOS because NMOS tox is usually smaller then the PMOS .

Also what i learn is diff from what i read here, let say we have a 1.2v and 2.5v source, i will use nmos for the 1.2v and pmos for the 2.5v source the reason is because pmos leakage is less then nmos and from the CV curve, the nmos will archieve stable C value at lower voltage so the nmos is more suitable for lower power source.
 

rania_hassan

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Hi, I'm not expert in the fabrication steps but I think the fine oxidation done for the gate is done for NMOS & PMOS together
& then the doping for the drain & the source for each one
the gate oxide can be used as a mask for the channel, so the gate oxide it self has a doping type it known as nploy or ppoly
please correct me if I'm wrong
best regards,
Rania
 

safwatonline

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NMOS , cause PMOS will have ESD isues where the gate is connected to the VSS PAD
 

safwatonline

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connecting the PMOS gate to the vss pad subject it to Spikes and since the gate is the weakest part of the MOS it may suffer from ESD spikes,having said that i must tell u that people do put the MOS gate to the vdd pad (power pad) in decoupling the direct vdd rail which should suffer from ESD issues too but people still do it.
 

safwatonline

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rania_hassan said:
Hi quanble,
Yes you are right, but still NMOS is preferred over PMOS as the parasitic channel resistance of NMOS is less than it for the PMOS which makes the time constant of NMOS is smaller that it for the PMOS & hence you can get better performance
Sorry for mixing it up .
best regards,
Rania

Added after 4 minutes:

Hi,
To get also smaller parasitic resistance for the decoupling cap, the length shouldn't be too small, which increase the gate resistance and also not to large
There is a perfect value for it dependent on the process used
best regards,
Rania

i am not sure but don't we need resistance to de-Q the Bond wire inductors
 

rania_hassan

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safwatonline said:
rania_hassan said:
Hi quanble,
Yes you are right, but still NMOS is preferred over PMOS as the parasitic channel resistance of NMOS is less than it for the PMOS which makes the time constant of NMOS is smaller that it for the PMOS & hence you can get better performance
Sorry for mixing it up .
best regards,
Rania

Added after 4 minutes:

Hi,
To get also smaller parasitic resistance for the decoupling cap, the length shouldn't be too small, which increase the gate resistance and also not to large
There is a perfect value for it dependent on the process used
best regards,
Rania

i am not sure but don't we need resistance to de-Q the Bond wire inductors

Hi,
The supply pad in any IC has a parasitics inductance, resistor & Capacitor, this can be considered as a series impedance with the circuits we will call the circuit supply as local supply
during switching like in CMOS Circuits, the supply should provide the circuits with large current which results in lowering the local supply & affecting the circuits performance.
The decoupling caps are used to provide the circuits with the large current needed during the switching, so it should be fast to overcome the situation said before.
I hope I clarified the point
best regards,
Rania
 

rfsystem

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I think ESD robustness is equal between NMOS and PMOS decoupling.

An item missing is the substrate noise coupling!

For the NMOS about 30% of the decoupling AC current is injected into substrate because of the Gate/Bulk-Cap. The PMOS collect the injected current in the NWELL which is connected to the decoupled VDD.

That should be enough reason to prefer this one.
 

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