Use of DCM in Altera FPGA (Cyclone II) Boards

[shom_show]

Hi all,

I am struggling with a program in Block diagram schematic way based on the usage of DCM for varying the frequency of a square wave signal so as to get 40 kHz square wave output. Can anyone suggest me how to construct the DCM block in Cyclone II for achieving the desired output.

Waiting eagerly for your response. Thanks in advance.

 

[FvM]

The clock processing units of Altera devices are named PLL rather than DCM.

Cyclone II PLLs have a minimal output frequency of 10 MHz, they can't generate 40 kHz, and it won't make much sense to generate a 40 kHz output signal by a PLL, even with newer devices like Cyclone III that support PLL post counter cascading and respective low output frequencies.

Instead you'll divide your input or PLL output clock with suitable counter.