use nc-verilog Simulation altera IP report erro

I used NC-Verilog5.1 to simulate ALTERA's IP(the DDR2 controller ,use quartus9.0 to generate) ,
but encouter erro :
ncvlog: *E,UMGENE (altera_mf.v,23972|5): An 'endgenerate' is expected [12.1.3(IE EE 2001)].

I find this erro from the file of altear_mf.v,the file used generate.
like below:
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate

I want to know how it happend, or the version of NC-VERILOG is too low.
How can I Solve this problem?? thanks all !!!