Use my library to synthesis ISCAS'89 benchmarks ?

[MAPLE LEAF]

ISCAS'89 benchmarks in verilog format are netlist, but they do not refer to a specific library. How can I synthesis the benchmarks with my own library?
Any suggestion?
Thanks.

 

[soloktanjung]

Why do you want to synthesis the benchmark? Because I think it is created for performance evaluation of architectures or anything that is based on the a standard netlist. It is not an architecture that you can synthesis.

Thanks.

 

[MAPLE LEAF]

Thanks for your reply.
I am doing a DFT(design for testability) experiment. I intend to verify my algorithm, which alters the connection of scan cells to reduce the test time and power, on the benchmarks. To evaluate the power, some library should be used, right? So, I wanna remap the cells onto my library.
Did I make myself clear?
Did I misunderstand the synthesis?

thanks.

 

[meldron1X]

Hi,

what do you mean with netlist? Actually, the ISCAS benchmarks are described as verilog RTL code. If this is the case then you need a compiler (e.g. "Design Compiler" from Synopsys or "RTL Compiler" from Cadence") and you have to put your library in the format required by your chosen compiler.

If you have a netlist in its real meaning (list of gates and nets) then you need the library that was used to generate that netlist. Then, with a help of a compiler, you can remap the old netlist to a new library (see above).

Cheers

 

[MAPLE LEAF]

Thank you for your reply.

actually, the benchmarks I got from Internet are described like this:

(in verilog format)


(in .bench format)

all gates and wires.

also, there are some other formats like .vhd, .blif, .cir, .pla, etc. can be found on the Internet. but I didn't find an RTL benchmark.

I successfully mapped the netlist to my library using Design Compiler. :smile:

 

[srinivastallapalli]

Hi,
How to synthesis ISCAS'89 benchmarks ? to simulate on spice for "dual level adaptive supply voltage system for variation resilience" The benchmark circuits are S526, S1423, and S5378 from ISCAS’89 suite in the 45-nm technology. and tell me how to get benchmark circuits in net.
Thank you very much...