Use Block RAM & ROM in FPGA

[rezvania]

Hello everyone
I want to use block RAM & ROM without using IP cores. Can I do it? if yes how can I do it?
Thanks for your responses

 

[ads-ee]

Hello everyone
I want to use block RAM & ROM without using IP cores. Can I do it? if yes how can I do it?
Thanks for your responses

You can by inference. You can see what I mean by looking up "inferring memory" in the following document for Altera. https://www.altera.com/literature/hb/qts/qts_qii51007.pdf

Regards

 

[axcdd]

Yes of course. There are plenty of examples in internet or you can check for vendor templates, or search in guides like this one:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/xst_v6s6.pdf

 

[rezvania]

Thanks,
But when I active using DSP48A cores (in SP6) it consume 450 DSP core from 50 totally core! and when I choose "Automatic", it doesn't use it. also I choose using of RAM and ROM but it doesn't use them. I must change in my code or I do other things? Thank you again

 

[TrickyDicky]

Why not post the code thats causing the problems?

 

[rezvania]

for example I use array for a ROM.

type ROM is  array (3 downto 0) of std_logic_vector(7 downto 0) := 
x"12",x"a3",x"b0", x"12";

and I want to implement this array by block ROM or RAM. But I don't know how to do this by XST. Could you help me?

 

[TrickyDicky]

thats not a rom, its not even correct VHDL (a type declaration cannot be initialised). Post the full code