USB 2.0 Implementation using Verilog

[kumar_eee]

usselmann rudolf asics usb

How to modelling a USB 2.0 using verilog?...

 

[atremp]

I think you should show more detailed information about this topic, for example: USB2.0 host controller? hub ? device controller or phy circuit.

 

[omara007]

hi kumar_eee

there is some already designed USB 2.0 IP's for free on the internet .. I know that of ASICs.ws .. designed by Rudolf Usselmann .. he has a website for himself called : www.asics.ws .. and he is hosting the Verilog IP itself on opencores under this link :
**broken link removed**

refer to this IP, maybe the documentation can be benfitial for u .. and the code too .. you need also to see the USB 2.0 standard document.

hope this helps