Usage of always inside a function in Verilog

[Bubs23]

Hi All,
I know this a very basic question i am posting.But i need correct answer for this.Can we write functions in verilog using always block.Can functions contain always block.Please explain it with an example.This is the question asked put to me in many interviews.

Thanks,
Bubs:-o

 

[alexan_e]

I think this link will help you

**broken link removed**
**broken link removed**

"A function can only be used if the module has at least one argument to be passed and requires only one argument returned from the function. A function can only be called from within an always or initial block within the module. The function is not allowed to contain either of these two statements, also any delay, event or timing control statements are forbidden. A function can use an input port they are allowed local variables as depicted in the page on syntax. Wires are not allowed and the complete function must be written using behavioral statements only. The actual manipulation of data in the function has to be placed between begin and end statements."

Alex

 

[deepthi_nach]

can we use always inside an always block?

 

[permute]

you can use more than one @() statement within an always block. more common for simulation.

 

[deepthi_nach]

how to declare bit vector signals in verilog?
like i need,
input [0:2] portin [0:2];
how can this declaration be done?