[Urgent]Timing question for simple d flip flop (DFF)

[AdvaRes]

[Urgent]Timing question

Hi members,

I have a question regarding timing constrain of a simple d flip flop (DFF) with an active low asynchronous reset. Consider tr the recovery time of this DFF, and th the hold its hold time. In data sheet we find all the timing constrains of this DFF. Actually, It looks like the hold time constrain is measured supposing the reset signal is inactive for a long time. What happen if the Reset and input data comes too close. I mean :

Let suppose that tr=0.5 th and that Reset and input changes at the same time (tr and th taken from datasheet). Is the new worst case constrain on the input I mean the real hold time th+tr or simply th ?

 

[dick_freebird]

[Urgent]Timing question

You would be concerned about the reset and the clock
active edge being too close; data by itself does nothing.

The reset release I suppose ought to precede clock by
"tr" to be safely passing clocked data, data ought to precede
clk by "ts" (setup, not mentioned) or lag by "th" (hold).

In the timing files / checks I have seen the two are criticized
independently and you get a flag for violating either one.

Reset after clk will always have the final say.