urgent-syncronous-fifo-using-dual-port-in-xilinx

[dymanojbabu]

hi
i tried synchronous fifo using dual port memory in xilinx... i wrote code in xilinx but i am getting some 'process error'.....i am not able to find....if any code is there help me....regarding memory i'm using one block ram memory... i am able to run the same codw in model sim software...

 

[TrickyDicky]

how about posting the code thats not working?

 

[dymanojbabu]

2sec
i wrote it in xilinx
xc3s200-4ft256
using one block ram memory
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fff is
Port ( clk : in STD_LOGIC;
ren : in STD_LOGIC; --read enable
wen : in STD_LOGIC; --write enable
wr_da : in STD_LOGIC_VECTOR (31 downto 0); --data into fifo
re_da : out STD_LOGIC_VECTOR (31 downto 0); --data out
reset : in STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC);
end fff;

architecture Behavioral of fff is
signal radd,wadd:std_logic_vector(3 downto 0); --write and read address
signal pre_opp_rd:std_logic; --previous opperations

type memory_type is array (0 to 15) of std_logic_vector(31 downto 0);--logic of memory
signal memory : memory_type :=(others => (others => '0'));

begin

process(reset,clk)
begin


if(clk'event and clk='1') then

if(reset='1') then --reset
radd<="0000";
wadd<="0000";
empty<='1';
full<='0';
pre_opp_rd<='1';

else
if(wen='1') then --writing the data into fifo
memory(conv_integer(wadd)) <= wr_da;
pre_opp_rd<='0';
wadd<=wadd+'1';
elsif(ren='1') then
re_da <= memory(conv_integer(radd)); --reading the data from fifo
pre_opp_rd<='1';
radd<=radd+'1';
end if;

if(wadd=radd) then
empty<=pre_opp_rd;
full<=pre_opp_rd;
else
empty<='0';
full<='0';
end if;
end if;
end if;

end process;
end Behavioral;

- - - Updated - - -

i also compiled same thing in model sim but i am not getting any error

- - - Updated - - -

help.............

- - - Updated - - -

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fff is
Port ( clk : in STD_LOGIC;
ren : in STD_LOGIC; --read enable
wen : in STD_LOGIC; --write enable
wr_da : in STD_LOGIC_VECTOR (31 downto 0); --data into fifo
re_da : out STD_LOGIC_VECTOR (31 downto 0); --data out
reset : in STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC);
end fff;

architecture Behavioral of fff is
signal radd,wadd:std_logic_vector(3 downto 0); --write and read address
signal pre_opp_rd:std_logic; --previous opperations

type memory_type is array (0 to 15) of std_logic_vector(31 downto 0);--logic of memory
signal memory : memory_type :=(others => (others => '0'));

begin

process(reset,clk)
begin


if(clk'event and clk='1') then

if(reset='1') then --reset
radd<="0000";
wadd<="0000";
empty<='1';
full<='0';
pre_opp_rd<='1';

else
if(wen='1') then --writing the data into fifo
memory(conv_integer(wadd)) <= wr_da;
pre_opp_rd<='0';
wadd<=wadd+'1';
elsif(ren='1') then
re_da <= memory(conv_integer(radd)); --reading the data from fifo
pre_opp_rd<='1';
radd<=radd+'1';
end if;

if(wadd=radd) then
empty<=pre_opp_rd;
full<=pre_opp_rd;
else
empty<='0';
full<='0';
end if;
end if;
end if;

end process;
end Behavioral;


2sec
i wrote it in xilinx
xc3s200-4ft256
using one block ram memory
i also compiled same thing in model sim but i am not getting any error