Urgent Slew & OCV clockgating jitter skew doubt

[gold_2007]

How do we arrive at slew , derate values .I mean based on what slew limit are derates values are decided ?R they depends on technology nodes ?

When clock gating helps in minimizing temperature then y we not consider clockgating helpful in minimizing leakage ?

What r the factors that affect jitter ?

why slew target should be met ?

Why we need to balance the skew ?

Why we need to minimize the insertion delay ?

What is the significance of global skew ?

How cell delay is calculated prects and postcts ?

Thanks in Advance

Gold

 

[iwpia50s]

I will attempt to answer your questions in order.

OCV derates are derived from process variation, you should get that from the fab or an FA group which has done the analysis.

Clock gating does not help leakage.

There is another post defining jitter, simple do a search.

CMOS consumes power during cell transition...the longer the slew the more power the cell consumes. A slew target is set to reduce power...and to prevent shoot thru.

Skew balancing is really the consequences of timing a design with ideal clocks. Ideal clocks means the STA tool assumes the clock arrives at each flop with no delay between them. Since this is not possible in the real world, a skew is defined based on the performance of the flops in the library.

Long insertion delays are susceptible to OCV, reduce the insertion delay and the impact of OCV can be reduced.

It is easier for a CTS tool to meet a single, global skew target than to try to meet individual skew between flops in a common path.

Cell delay is not impacted based on pre and post cts. Only the cells in the clock path are different.

 

[h.edaboard]

I tend to agree with iwpia50s, except about the question "why slew target should be met ? "

what I see is, if slew target is not met, then the cell delay will be calculated in the range which is out of the library defined, which means there's may be a big mismatch between the calculated value and the actual value, this would potentially lead to timing failure.

 

[iwpia50s]

h.edaboard is correct, however, my assumption was that the slew was within range of the table, just not meeting the slew target.

 

[h.edaboard]

hi iwpia50s,

My assumption was that the 'slew target' is the library slew target from the ASIC vender, of course, you are right, if additional slew target given which is even more strict than the library range, a violation of the target (slew might still meet library slew target) could lead to more power consumption or even worse, suffer a SI problem.

 

[singhvi]

cell delay can be calculated from the library
input transition and output load. or SDF will contain all the cell delay information