Urgent help needed !!

[berko3000]

Hi guys,
I have a problem with the simulation of my full adder cell layout. I drawed its layout in Magic but when I try to simulate it using Hspice and Awanwaves I'm getting spikes which I circled in red in this link:

**broken link removed**

How can I fix it?

thanks

Added after 5 hours 25 minutes:

any idea??

 

[tomanderson]

A delay for output sum might solve.
For vhdl ex:

sum <= ( a xor b ) afte 5 ns ;
carry <= ( a and b ) after 5 ns ;

 

[berko3000]

A delay for output sum might solve.
For vhdl ex:

sum <= ( a xor b ) afte 5 ns ;
carry <= ( a and b ) after 5 ns ;

I'm not using VHDL for this: only Magic Layout and Hspice for generating spice file and Avanwaves for waveforms. Do you recommend another idea in the layout or in hspice?

 

[santhosh.mandugula]

hi..
Input signal A and B are rising from 0 to 1 (two signals are in undefined state at a time), because of that you are getting a spike at that inputs. Try to avoid such input states while giving the inputs then you won't get any spikes. So at this undefined states of input the spike (unwanted variation) came only for SUM and there is no spike in CARRY because there is a change of state.