Urgent help needed to code a verilog file. Pls help.

[chuggington]

A very basic question, because I have 0 knowledge about coding. How can you create a simple verilog file that calls for a memory ? Basically I just need to specify the module and then instanatiate. this is just to see the lef. So no need of proper instanatiation. my memory lef has around 300 input and output pins/

I have done

module (); # specified all inputs and outputs.

Now how do i call it ?

 

[oratie]

module sram (addr, din, dout, clk); # specified module and interface for your memory
input addr, din, clk;
output dout;
endmodule

module top (); # just a name of upper hierarchy level
wire addr_wire;
sram u1 (.addr(addr_wire), .din(datain_wire), .clk(clock), .dout(dataout_wire); # instance name u1 of early specified memory sram
endmodule

 

[chuggington]

Thanks, Oratie !