Ata-Va
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Hi buddy,as Iam new to vhdl I would be very thankful if sb helps me writing a code describing these two lines
where 'Data_In' is a one bit length data and 'Gray_Coded_Data' is std_logic_vector(19 downto 0) and 'i' is integer range 0 to 19;
process( falling_edge(Absolute_Encoders_Clock))
if ( falling_edge(Absolute_Encoders_Clock) ) then
Gray_Coded_Data := ( i => Data_In ,others=>unaffected);
i := i+1;
end if;
actually i thought of shift right logically(srl) but it didn't work much to my surprise
sth like the blove code in matlab
for i=1:1:20
if (falling_edge=1)
Gray_Coded_Data(i)=Data_In ;
i := i+1;
end if;
end;
thx every body
where 'Data_In' is a one bit length data and 'Gray_Coded_Data' is std_logic_vector(19 downto 0) and 'i' is integer range 0 to 19;
process( falling_edge(Absolute_Encoders_Clock))
if ( falling_edge(Absolute_Encoders_Clock) ) then
Gray_Coded_Data := ( i => Data_In ,others=>unaffected);
i := i+1;
end if;
actually i thought of shift right logically(srl) but it didn't work much to my surprise
sth like the blove code in matlab
for i=1:1:20
if (falling_edge=1)
Gray_Coded_Data(i)=Data_In ;
i := i+1;
end if;
end;
thx every body