Urgent help needed for Verilog code

[wik.haider]

Hi all.
I am trying to implement Integer division by this algorithm in verilog:

1. Put dividend in lower half of register and clear upper half. Put
divisor in divisor register. Initialize quotient bit counter to zero.
2. Shift dividend register left one bit.
3. If difference positive, shift 1 into quotient and replace upper half
of dividend by difference. If negative, shift 0 into quotient.
4. If fewer than m quotient bits, repeat from 2.
5. m bit quotient is an integer, and an m bit integer remainder is in
upper half of dividend register.

and have written the following code but cannot get it to work. I am a beginner in verilog and need urgent help to rectify my mistakes. Any help would be greatly appreciated

Code:

module div(clk, Dividend, Divisor, Quotient, Remainder);

input clk;
input [7:0]Dividend;
input [7:0]Divisor;
output [7:0]Quotient;
output [7:0]Remainder;


reg [15:0] sftIn;
reg [7:0] dvsr;
reg [7:0] quot;

reg [7:0] temp;
reg [2:0] counter;

reg[3:0]i;

initial
begin
sftIn = {Dividend[7:0], 8'b00000000};
//put dividend in lower half of register and clear upper half
dvsr = Divisor;
//put divisor in divisor register
quot = 8'b00000000;
//initialize quotient bit counter to zero
end

always @ (posedge clk)
begin


for(i = 0; i < 8; i = i + 1)
begin
sftIn = sftIn << 1;
//shift dividend register left one bit

if(sftIn - dvsr > 0)
//is difference positive
begin
quot = quot << 1;
quot[0] = 1;
//shift one into quotient
sftIn[15:8] = (sftIn - dvsr);
//replace upper half of dividend by difference
counter = counter + 1;
end
else if(sftIn - dvsr < 0)
//if difference negative
begin
quot = quot << 1;
quot[0] = 0;
//shift quotient and put 0
counter = counter + 1;
end
end

end //end of module

assign Quotient = quot;
assign Remainder = sftIn[15:8];

endmodule