urgent help need for Constraint manager in Allegro 16.3

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Hi ,
i am using Allegro 16.3 , i want to do work on my constraint manager ,i looked in allegro help but not find it much helpfull .
pls can anyone provide any doc. or ppt to understand the conastainr manager rule setting for Diff pair ( its length matching ) and other relative propogation delay matching ,pin pairs ,

Thanks in advance
 

thanks Kapil ,

I am using DDR 2 and here i want length match for Address and make T points from Controller to 2 Memory Devices and length match it .there are Diff pairs also to match upto 5 mils ,so i need help to update all in Constraint manager .

Thanks in advance
 

Hi JACK,
For Electrical constraint setting make Class for (90 or 100 E )Differential pair (Name may be like that Diff_90E) and add the all the differential pair .
 

Hi ,

pls need help for DDR 2 ,Address Tpoint creation in Allegro 16.3 , i am also tyring SigXplorer , pls help
 

hi jack,
which net r u want to make t-point select that net using net scheledul and then right click insert T point
 

hi jack
if u have another brd file just export the tech.file, and import ur latest file.

thanks & regards,
Mareeswran.k
 

hi ,

thanx for the reply Mareeswran . I want to implement rules in Constraint Manager for DDR 2 .I have gone through the help file and books ,but i do not find interactive help for how to set Length matching for all Data and Address/Control lines and how to set T-points for Address/Control and their Lenght matching in Allegro 16.3 .
Pls help , i need it very urgent .If their is any paid training ( Online) pls suggest .I have all Cadence Help data and Books ,so i am looking something practical .

Thanks
 

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