Urgent - FSM Code Not recognized by NCElab. Why?

[raghavathej]

Hi,

This is sample Code which is not recognised by Cadence NCelab.
Why So?

Here is the part of the Code :-
always @(posedge CLK_I or posedge RST_I) begin
if (RST_I)
rx_latch_flag <= 1'b0;
else if ((c_status == ST_TRANS) && (n_status !== ST_TRANS))
rx_latch_flag <= 1'b1;
else if (rx_latch_flag)
rx_latch_flag <= 1'b0;
end

always @(posedge CLK_I or posedge RST_I)
if (RST_I)
clock_cnt <= 0;
else if (clock_cnt == CLOCK_SEL || (n_status == ST_IDLE))
clock_cnt <= 0;
else
clock_cnt <= clock_cnt + 1;

always @(posedge CLK_I or posedge RST_I) begin
if (RST_I)
c_status <= ST_IDLE;
else
c_status <= n_status;
end

wire [5:0] ACTUAL_MAX = (CLOCK_POLARITY == CLOCK_PHASE) ?
DATA_LENGTH - 1 :
DATA_LENGTH;

always @(negedge CLK_I or posedge RST_I)
begin
if (RST_I)
n_status <= ST_IDLE;
else
case(c_status)
ST_IDLE: if (pending_data)
n_status <= ST_LOAD;
else
n_status <= ST_IDLE;
ST_LOAD: begin
if (DELAY_TIME == 0)
n_status <= ST_TRANS;
else
n_status <= ST_WAIT;
end
ST_WAIT: begin
if ((clock_cnt == CLOCK_SEL) && (data_cnt == DELAY_TIME - 1))
n_status <= ST_TRANS;
else
n_status <= ST_WAIT;
end
ST_TRANS: begin
if ((clock_cnt == CLOCK_SEL) &&
(data_cnt == ACTUAL_MAX) &&
(SCLK_MASTER != CLOCK_POLARITY))
n_status <= ST_TURNAROUND;
else
n_status <= ST_TRANS;
end
ST_TURNAROUND: begin
if (clock_cnt == CLOCK_SEL)
if (INTERVAL_LENGTH)
n_status <= ST_INTERVAL;
else
n_status <= ST_IDLE;
end
ST_INTERVAL: begin
if ((clock_cnt == CLOCK_SEL) && (data_cnt == INTERVAL_LENGTH))
n_status <= ST_IDLE;
else
n_status <= ST_INTERVAL;
end
default: n_status <= ST_IDLE;
endcase
end

always @(posedge CLK_I or posedge RST_I) begin
if (RST_I)
data_cnt <= 0;
else if ((c_status == ST_WAIT) && (clock_cnt == CLOCK_SEL) && (data_cnt == DELAY_TIME - 1))
data_cnt <= 0;
else if ((c_status == ST_TRANS) && (clock_cnt == CLOCK_SEL) && (data_cnt == ACTUAL_MAX) && (CLOCK_POLARITY != SCLK_MASTER))
data_cnt <= 0;
else if ((c_status == ST_INTERVAL) && (clock_cnt == CLOCK_SEL) && (data_cnt == INTERVAL_LENGTH))
data_cnt <= 0;
else if (((c_status == ST_WAIT) && (clock_cnt == CLOCK_SEL)) ||
((c_status == ST_TRANS) && (clock_cnt == CLOCK_SEL) && (CLOCK_PHASE != SCLK_MASTER))||
((c_status == ST_INTERVAL) && (clock_cnt == CLOCK_SEL)))
data_cnt <= data_cnt + 1;
end

reg wait_one_tick_done;
always @(posedge CLK_I or posedge RST_I) begin
if (RST_I)
wait_one_tick_done <= 1'b0;
else if (CLOCK_PHASE == CLOCK_POLARITY)
wait_one_tick_done <= 1'b1;
else if ((c_status == ST_TRANS) && (clock_cnt == CLOCK_SEL) && (data_cnt == 1))
wait_one_tick_done <= 1'b1;
else if (data_cnt == 0)
wait_one_tick_done <= 1'b0;
end

always @(posedge CLK_I or posedge RST_I) begin
if (RST_I) begin
MOSI_MASTER <= 0;
tx_shift_data <= 0; end
else if (((c_status == ST_LOAD) && (n_status == ST_TRANS)) ||
((c_status == ST_WAIT) && (n_status == ST_TRANS))) begin
MOSI_MASTER <= SHIFT_DIRECTION ? reg_txdata[0] :
reg_txdata[DATA_LENGTH-1];
tx_shift_data <= SHIFT_DIRECTION ? {1'b0, reg_txdata[DATA_LENGTH-1:1]} :
{reg_txdata, 1'b0};
end
else if ((c_status == ST_TRANS) && (clock_cnt == CLOCK_SEL) && (CLOCK_PHASE ^ SCLK_MASTER) )
if (wait_one_tick_done) begin
MOSI_MASTER <= SHIFT_DIRECTION ? tx_shift_data[0] :
tx_shift_data[DATA_LENGTH-1];
tx_shift_data <= SHIFT_DIRECTION ? {1'b0, tx_shift_data[DATA_LENGTH-1:1]} :
{tx_shift_data, 1'b0};
end
end

always @(posedge CLK_I or posedge RST_I)
if (RST_I)
reg_trdy <= 1;
else if ((c_status != ST_TRANS) && (n_status == ST_TRANS))
reg_trdy <= 1;
else if (reg_wr && dw04_cs && SPI_ACK_O)
reg_trdy <= 0;

always @(posedge CLK_I or posedge RST_I)
if (RST_I)
reg_toe <= 0;
else if (!reg_trdy && reg_wr && dw04_cs && SPI_ACK_O)
reg_toe <= 1'b1;
else if (reg_wr && dw08_cs && SPI_ACK_O)
reg_toe <= 1'b0;

always @(posedge CLK_I or posedge RST_I)
if (RST_I) begin
reg_rrdy <= 1'b0;
reg_roe <= 1'b0; end
else if ((c_status == ST_TURNAROUND) && (clock_cnt == CLOCK_SEL)) begin
if (reg_rrdy)
reg_roe <= 1'b1;
else begin
reg_rrdy <= 1'b1;
end
end
else if (reg_rd && dw00_cs && SPI_ACK_O) begin
reg_rrdy <= 1'b0;
reg_roe <= 1'b0; end

always @(posedge CLK_I or posedge RST_I)
if (RST_I)
reg_tmt <= 1'b1;
else if ((c_status != ST_IDLE) || pending_data)
reg_tmt <= 1'b0;
else
reg_tmt <= 1'b1;

end



Thanks..Please let me know the solution.