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[Urgent] FIFO Buffer and Functional Simulation

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OvErFlO

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What's wrong in this code... when I do functional Simutation I receive this error from model sim :

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 852200 ps Iteration: 1 Instance: /wave_generator_3ch_tb/uut/cu2_u3

this is the code :
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity buffer_fifo_32bit is
  Port ( 
	  clk      : in  std_logic;
	  rst      : in  std_logic;

	  put_data : in  std_logic;
          get_data : in  std_logic;
	  empty    : inout std_logic;
	  full 	   : inout std_logic;
	  
          data_in  : in  std_logic_vector (31 downto 0);
          data_out : out std_logic_vector (31 downto 0));

end buffer_fifo_32bit;

architecture arch_32bit of buffer_fifo_32bit is

  component ram_dualport is
      Port ( clk : in std_logic;

             we : in std_logic;
             data_in : in std_logic_vector(31 downto 0);
             W_add : in std_logic_vector(7 downto 0);

             R_add : in std_logic_vector(7 downto 0);
             data_out : out std_logic_vector(31 downto 0));
  end component;

  signal addr_out   : std_logic_vector (7 downto 0) := "00000000";
  signal addr_in    : std_logic_vector (7 downto 0) := "00000000";
  signal nelementi  : std_logic_vector (7 downto 0) := "00000000";
  signal we         : std_logic;

begin

	with nelementi select
		empty <= '1' when "00000000",
			    '0' when others;
	
	with nelementi select
		full  <= '1' when "11111111",
			    '0' when others;

	buffer_u1: process (clk, rst, addr_in, addr_out, nelementi, get_data, put_data) 
	  variable v_addr_in, v_addr_out, v_nelementi : std_logic_vector (7 downto 0);
	begin
		if (rst = '1') then
		  v_addr_in	:= (OTHERS => '0');
		  v_addr_out	:= (OTHERS => '0');			
		  v_nelementi	:= (OTHERS => '0');
		  addr_in	<= (OTHERS => '0');
		  addr_out	<= (OTHERS => '0');			
		  nelementi	<= (OTHERS => '0');

		elsif (rising_edge(clk)) then
		  if (put_data = '1' AND full='0') then
		    v_addr_in := v_addr_in + "00000001";
		    v_nelementi := v_nelementi + "00000001";
		  else
		    v_addr_in := v_addr_in;				
		  end if;
		
		  if (get_data = '1' AND empty='0') then
		    v_addr_out := v_addr_out + "00000001";
		    v_nelementi := v_nelementi - "00000001";
		  else
		    v_addr_out := v_addr_out;
		  end if; 

		  addr_in <= v_addr_in;
		  addr_out <= v_addr_out;
		  nelementi <= v_nelementi;
		end if;	

	end process;

	we <= put_data;
	ramdualport : ram_dualport port map (clk => clk, data_in => data_in, we => we, W_add => addr_in, R_add => addr_out, data_out => data_out);

end arch_32bit;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ram_dualport is
    Port ( 
          clk : in std_logic; we : in std_logic;           
	  data_in : in std_logic_vector(31 downto 0);
          W_add : in std_logic_vector(7 downto 0);
           
	  R_add : in std_logic_vector(7 downto 0);
          data_out : out std_logic_vector(31 downto 0));
end ram_dualport;

architecture architecture_256x32 of ram_dualport is

  type ram is array (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (31 downto 0);
  signal ram_256 : ram (0 to (2**8));

begin

  ram_dualport: process (clk,R_add) 
  begin
    if ( rising_edge(clk) ) then
      if (we = '1') then
        ram_256(conv_integer(W_add)) <= data_in;
      end if;
    data_out <= ram_256(conv_integer(R_add));
    end if;
          
  end process;
	
end architecture_256x32;


thanks
 

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