Urgent: eye diagram plotting using hspice

[brrk007]

Urgent: eye diagram

Hi all,

I working on some stuff related to networks on chip and my work needs me to plot the eye diagram. I came to know the way to plot the eye diagram using hspice but am confused what actually needs to be plotted (I mean which value). Is it the power of the signal at the receiver end/power of the signal at the transmitter end , or anything else. Please give me a hint on what to be plotted so that I can continue my work. If possible, cite any sources where I can get exhaustive information.


Thanks
Ravi

 

[Halcon]

Re: Urgent: eye diagram

Hi Ravi,

Here is an example of an eye diagram i took (Comparaison of two solutions).

The one above is showing much less clock jitter than the one below.

You make these kind of diagrams by triggering on the CLK and measuring the received bit stream.

If the bits are overlapping then you are experiencing high Inter symbol interference (ISI).

Put another way: If the eye is open then you have low ISI and when the eye begins to close you have higher chance of bit reconstruction error.