(URGENT) Current Mirror

[saad]

Hi,
I am simulating current mirror circuit with emitter coupled pair in PSpice as follows.

Current through collector of Q1 is 490µA as expected (Ic1=Vcc-VBE1)/R) but it does not work as current mirror. I am attaching the waveform of Ic2 (i.e. collector current of Q2) its far less than 490µA (nearly zero i.e. 74pA)

Can anyone pointout my mistake? or its the error of my PSpice? or its error of PSpice in general?

Please if you can answer quickly.

Thanks,
Saad

 

[unkarc]

Hi,

I think Q5 and Q6 are closed and this is the problem? To check this, omit these two transistors and V3, and simply connect the collector of Q2 to V1 through a resistor and see the current (should be around 490uA).

unkarc

 

[cellphone]

The base of Q5 and Q6 are floating. That is there is no current path to go to base. Since these are current driven devices the base cannot be floating when the operate. Put a voltage source from the base of Q6 to gnd and likewise for Q5. Or, connect gnd to the negative terminal of Q6. That way Q5 is off and you have a path to Vdd through Q6.

Or, do waht unkarc says. that should work too.

 

[saad]

hello,
I have to use Emitter coupled pair with this current mirror circuit. I cannot use the current mirror alone.

Also, this circuit is operating in differntial input mode (rather than single ended input mode) that is why the base (of Q5 and Q6) seem floating. In reality it is not floating.

If you can see anything else. please let me know.

Thanks.

 

[unkarc]

The purpose of my suggestion was for you mainly to test the normal current mirror operation in your simulator. Have you tested it??

I agree with cellphone, that is also what I guessed: the diff. transistor pair do not get correct DC bias from V3! To check this, omit V3 and bias base 5 and base 6 via two separate resistors from V1, ok?

 

[nxing]

that is because of the floating base of Q5 and Q6

 

[jonashat]

hello,
Also, this circuit is operating in differntial input mode (rather than single ended input mode) that is why the base (of Q5 and Q6) seem floating. In reality it is not floating.

A differential mode circuit is the one that only responds to the signal difference between its two terminals.

Still you have set the voltage at the base of Q5 and Q6 to some value with respect to the ground of the circuit.

Maybe split the 1V diff battries to two 0.5V batteries in series and then add another hook up another voltage source (common mode) between those two.

 

[saad]

Thanks for the replies.

In PSpice, the differential voltage sources of this form do not make the nodes floating. Though the difference between the two terminals of V3 is 1V but the base of transistors Q5,Q6 are at very high voltage (when simulated in PSpice) may a voltage in excess of 60KV.

Also, the current mirror works fine alone. I want this current mirror to act as the bias current of the Emitter-coupled pair at its top (constituted by Q5,Q6). neither i can remove the emitter coupled pair nor i can change the input-mode (because it is the requirement of the design).

Any other suggestions are welcomed.

Saad

 

[unkarc]

Hi,

Please try to understand that your Q5 and Q6 transistors are still closed so their collector current cannot flow!!!

This is because your V3 voltage source --even if you choose it to be 1.2-1.3V instead of the present 1V-- inherently gives a negative bias to one of the two bases:

If you place the positive pole of V3 onto Q5's base and its negative pole onto Q6's base, or just opposite case what is shown in your schematics now it does not matter: there can NEVER be any forward bias to these two transistors from V3. WHY?

Imagine two diodes (the actual base-emitter diodes of Q5 and Q6) are connected in series from V3 point of view: one of the diodes' cathode connects to the other diode's cathode (this is the common center point i.e. the two emitters where the two cathodes are joined, and the two anodes of these two diodes are the bases of Q5 and Q6).

Now how can you forward bias either or both of these two diodes with V3 in your present schematics??? It would only be possible if the connections were cathode-anode in the common center point and NOT cathode-cathode like it is now, right?

Consider a Darlington pair, the two transistors' base-emitter diodes are in series (their common point is always consists of a cathode-anode i.e. an emitter-base connection) and they need at least 1.2V forward bias to operate.

Hope this helps.

unkarc

 

[hr_rezaee]

Hi
Use a enough input common mode voltagefor Q6 and Q5, then use diff. voltage as input diff. mode voltage.
Q6 and Q5 are off.
regards

 

[saad]

How much?

 

[hr_rezaee]

Hi
Vbe+Vce-min=0.7+0.2=0.9v
connect base of Q5 to Vcm+vd/2 and base of Q6 to Vcm-Vd/2.
Vcm-min=0.9v and Vd=input diff. desired voltage
regards

 

[saad]

Actually the design requires a single source to be connected (in differential mode) to the inputs of emitter coupled pair. Consider it as a realtime requirement. I can split the source into two for the sake of simulations but the design requirement is such that it does not permit me to do so, when i will be making the real circuit.

Isnt there any other solution to the problem?

Thanks.

 

[amriths04]

connect the the -ve terminal of v3 to ground. and it's +ve terminal to the base directly and also connect the same positive terminal to the other transistor's base through an inverter. hope this will solve your analysis purpose.

 

[hr_rezaee]

Hi
I'm sorry
all diff. pairs need inputcommon mode voltage.
so you must connect it but in any way that you can.
base of Q5 and Q6 must have a DC voltage about 0.9v to work correctly.
regards

Added after 1 hours 38 minutes:

................................VCC
...................................|
...................................>
...................................>
...................................>
...................................|
...................+Vdiff--||--|----Vbase6
...................................|
...................................>
...................................>
...................................>
...................................|
................................GND


................................VCC
...................................|
...................................>
...................................>
...................................>
...................................|
................... -Vdiff--||--|----Vbase5
...................................|
...................................>
...................................>
...................................>
...................................|
................................GND


or if you have a DC diff. input use this:
................................VCC
...................................|
...................................>
...................................>
...................................>
...................................|
..............+Vdiff--^^^--|----Vbase6
...................................|
...................................>
...................................>
...................................>
...................................|
.................................GND

regards

 

[rajanarender_suram]

You dont have input common mode voltage for q5 qnd q6...that the reason the simulations are not working properly