the_phoenix
Newbie level 6
Hey guys...well, im in a soup....and i need help quite urgently!!!
I had a post about this same topic b4...quite sometime back...
It is about this async system that i plan to design. The idea was to design an async ALU....a simple one albeit...but one which cud demonstrate the gr8 possibilities with async logic design over the sync desing...
Well...all thru, i had been thinking on lines of developing a totally async ALU...but now...i have hit upona novel way of realising async operation by tweaking an existing sync architecture...
I plan to develop an ALU block...add/sub, multiplier,divider,logic,shifter included...and use a set of REQ/ACK lines...generated from within an ALU...which cud b used to control the clocking network...turn it on/off i mean....something, which cud maybe, eliminate the waste of wait cycles...
Now, from my rater basic research about all this..i realise that this wud need an onboard clock....
now, i need some help reagrding this...plz try n think this over n make sense abt whether i cud make this work....wud it be okay to concentrate merely on the ALU part and present the project as a work on how one cud tweak an exisitng sync arch to an asycn arch ....does it sound ok..im a UG student...n this is my firts serious proj....i plan to include 16 opcodes...for all the ALU operations....
please help me on this .....any help wud b greatly appreciated...
i'd be using VHDL tools....
i need help on how to time the wait periods in the REQ/ACK cycles...depending on the operation being carried out..viz. divide wud need the max time...how do i achieve the same....
thanks anyway....
I had a post about this same topic b4...quite sometime back...
It is about this async system that i plan to design. The idea was to design an async ALU....a simple one albeit...but one which cud demonstrate the gr8 possibilities with async logic design over the sync desing...
Well...all thru, i had been thinking on lines of developing a totally async ALU...but now...i have hit upona novel way of realising async operation by tweaking an existing sync architecture...
I plan to develop an ALU block...add/sub, multiplier,divider,logic,shifter included...and use a set of REQ/ACK lines...generated from within an ALU...which cud b used to control the clocking network...turn it on/off i mean....something, which cud maybe, eliminate the waste of wait cycles...
Now, from my rater basic research about all this..i realise that this wud need an onboard clock....
now, i need some help reagrding this...plz try n think this over n make sense abt whether i cud make this work....wud it be okay to concentrate merely on the ALU part and present the project as a work on how one cud tweak an exisitng sync arch to an asycn arch ....does it sound ok..im a UG student...n this is my firts serious proj....i plan to include 16 opcodes...for all the ALU operations....
please help me on this .....any help wud b greatly appreciated...
i'd be using VHDL tools....
i need help on how to time the wait periods in the REQ/ACK cycles...depending on the operation being carried out..viz. divide wud need the max time...how do i achieve the same....
thanks anyway....
