[SOLVED] URGENT! 4-bit up counter

[karthiga05]

This is my current 4-bit count up counter. Im still stuck at the portmapping part. would really love ure help! thanks. im not sure whr c_out and cin goes to. im not sure if this is the right method too.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(countut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter;

architecture behav_counter of ha is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b: in std_logic:='0';
cin:in std_logic;
sum, cout: out std_logic);
end component;

signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal s: std_logic_vector(3 downto 0);
signal cout: std_logic;

--configuration specification
for ha1, ha2: ha use entity work.ha(rtl);
for fa1: fa use entity work.fa(fa_behav);

begin

counterrocess(clk, reset)
begin
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then

ha1:ha port map(a => a(3), b => b(3), sum => s(3), c_out => cout(3));
ha2:ha port map(a => s(3), b => b(2), sum => s(2), c_out => cout(2));
fa1:fa port map(a => , b => , cin => , sum => ,cout => );

end if;
end process;

count <= s;

end behav_counter;

 

[dcreddy1980]

one simple thing, you are giving a,b as inputs to HA, but where are you generating these signals?

First list down how you wanna do, then it will be clear.

 

[karthiga05]

am i right to use 2 half adders and 1 full adder??

---------- Post added at 11:16 ---------- Previous post was at 10:46 ----------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(countut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter;

architecture behav_counter of ha is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;


signal a,b,c1,c2,c3,c4,s1,s2,s3,s4:std_logic;

begin

counterrocess(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
c <= (others => '0');

elsif clk'event and (clk='1') then

--configuration specification
for ha1, ha2, ha3, ha4: ha use entity work.ha(rtl);

ha1:ha port map(a => a, b => b, sum => s1, c_out => c1);
ha2:ha port map(a => s1, b => b, sum => s2, c_out => c2);
ha3:ha port map(a => s2, b => b, sum => s3, c_out => c3);
ha4:ha port map(a => s3, b => b, sum => s4, c_out => c4);

end if;
end process;

count <= s;

end behav_counter;

this is what i can come up with.

 

[TrickyDicky]

Dont put entities inside processes. Entities are not functions like in C. They are actual blocks that run in parrellel to all code. So port maps do not belong in a process.