Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[UPF]How to merge power state tables from lower-level block to top-level?

Status
Not open for further replies.

LanYieL

Newbie level 1
Joined
Dec 6, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,287
Critical path locates at a sub-block which occupies a seperate power domain. So I use hierarchical flow during synthesis. First, synthesize the sub-block with its own upf and write out subblock.ddc. Then during top synthesis, read top RTL and subblock.ddc, and propagate power supply data to top. After compile I cannot get the power intent information of subblock.upf from top.upf' generated by tool. Anyone knows how to fix this?

Thanks,
LanYieL
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top