Undesiderated 1-bit latch

[HyperText]

Hi, I'm programming a N-bit non-restoring divider, but I faced a little problem.

I have an Operative Part (combinatorial) and a Control Part (Finite State Machine).
The Control Part has a 2 processes FSM, 1 for updating the next state and 1 for the "state sequence".

	update: 	process(clk_in, next_state)
			begin
				if rising_edge(clk_in) then
					current_state <= next_state;
				end if;
			end process;

And this is the second process:

	control:	process(current_state, start, S_in, counted)
				variable sub_tmp : STD_LOGIC := '0';
			begin
                                [...]
				sub <= sub_tmp; -- sub is an output signal of my entity that goes in the Operative Part

				case current_state is
					when idle =>
						if start='1' then
							next_state <= init;
						else
							next_state <= idle;
						end if;
					
					when init =>
                                                -- [...]
						next_state <= subtract;
					
					when subtract =>
						en_A <= '1';
						sub_tmp := '1';
						next_state <= test;
					
					when test => -- shift
						en_Q <= '1';
						
						if S_in='0' then
							sub_tmp := '1';
						else
							sub_tmp := '0';
						end if;
						
						if counted=N/2-1 then
							next_state <= finished;
						else
							next_state <= operation;
						end if;
					
					when operation =>
						en_A <= '1';
						next_state <= test;
					
					when finished =>
						stop <= '1';
						next_state <= idle;
				end case;
			end process;

As you can see, I need to change the value of the sub ONLY in 2 cases (subtract and test), while I don't have to change in the other cases.

The problem is that when I try to synthesize this code it turns out that sub_tmp is a LATCH, but I don't want a latch.
I need to do something like this:
state 1 => set sub to '1' or '0' (depending on another input)
state 2 => do other operations (but sub must remain the value set before) and return to state 1
etc...

To clarify more: in certain states of my FSM (not all of them) I set the value of a variable (let's call it sub_tmp). In other states I don't change its value. Then let's say I have an output PIN called "sub_out". Now, independently of the variable value, I want to output its value to this pin (sub_out <= sub_tmp; or similar).

What am I missing?


Thanks

 

[FvM]

state 2 => do other operations (but sub must remain the value set before)

That's what we call a latch, if done in asynchronous sequential code. So apparently latch synthesis is wanted.

A latch can however bring up a problem of not keeping the "value set before" correctly when the state changes. Thus you'll possibly want a synchronous register instead.

The usual understanding of the two-process state machine construct is however that the asynchronous part only contains pure combinational code without latches. This involves that present state can be fully decoded to output signals, without depending on previous states.

 

[HyperText]

Thanks, you enlightned me ^_^
I rewritten my FSM and now it "works", except a warning that I receive in the Implementation phase.

Phase 11 : 0 unrouted; WARNING:Route:455 - CLK NetC/current_state_FSM_FFd4 may have excessive skew because

(Yes, because... nothing, at least seems so)

Here is the incriminated part: https://pastebin.com/N53F6Fhz

What am I doing wrong? That's the only warning I receive :|


Thanks