Understanding VHDL code snippet logic ?

[syedshan]

Dear all,

I am trying to understand a design code where operation starts after trigger, I have a little propblem
in understanding WHY a certain operation is done in the code...

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Code VHDL - [expand]
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...
port(...
trigger_to_fpga  : in std_logic; -- external trigger to start data capture from ADC
...
);
...
signal ext_trigg_pipe   :std_logic_vector(10 downto 0);
signal ext_trigg_edge  :std_logic; --This signal is the reference for the operations to start
...
...
process (rst, clk)
begin
  if (rst = '1') then
 
    ext_trigg_edge  <= '0';  
    ext_trigg_pipe         <= (others =>'0');
 
  elsif (rising_edge(clk)) then
 
    --couple of deglitching register
    ext_trigg_pipe <= trigger_to_fpga & ext_trigg_pipe(10 downto 1);
 
    if (ext_trigg_pipe(1) = '1' and ext_trigg_pipe(0)='0') then
      ext_trigg_edge <= '1'; --This signal is the reference for the operations to start
    else
      ext_trigg_edge <= '0';
    end if;
 
  end if;
end process;

---

Here I understand that the purpose is to capture the external trigger removing the glitches or uncertrainities in the external trigger,
but what I dont understand is the usage of ext_trigg_pipe variable's size...Why is it 11 bit, Any suggestion...

Also if I have multuple clock domain, can I replicate (changing signals and clock of course) this to other clocks or do I have to change the
ext_trigg_pipe size.

Many thanks
Shan

 

[TrickyDicky]

I assume trigger_to_fpga is asynchronous or on another clock domain? For this you will need at least a double register to capture it without metastability. If this is the case, the edge should be checked on 1 and 2, not 0 and 1, as 0 could be metastable.

If the above is not the case, then it could have just been set up as a shift register to align it with other control signals and then not used. The synthesisor will just trim any unused registers.

 

[syedshan]

Thank you for your reply,


Yes you guess right, trigger is totally asynchronous.

For this you will need at least a double register to capture it without metastability. If this is the case, the edge should be checked on 1 and 2, not 0 and 1, as 0 could be metastable.

Pardon me, can you explain this thing what you define about bits 1,2 and 0. Can you tell me the logic behind.
Also the concatenation is just the shift register, hence it is there to remove the metastability, right?

Simply put, it is an asynchronous edge detection, right?

Bests,
Shan

 

[std_match]

It is OK to use bit 0 for the edge detection since the new data is clocked into bit 10.
It is enough with 3 bits for synchronization and edge detection, so your circuit is just a synchronization + extra delay + edge detection.