I must confess that I rarely use timing analysis for IO, only regularly for core logic.
But it's supported by the vendor timing analysis tools. They have libraries including IO time delays and can check the design margins against your requirements, also adjust routing and programmable IO delays (if available) to some extent.
But if a design has plenty of IO timing margin by nature, you don't need to check or adjust anything.
Rysc has written a great user guide for Altera TimeQuest , it should also apply to other STA tools using the Synopsys design constraints language.