Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Understanding the C54x Memory Maps and Examining an Optimum

Status
Not open for further replies.

kudjung

Member level 4
Joined
Jan 17, 2003
Messages
77
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
733
Hello All,

Did anyone use to read TI appnote. SPRA607(with the title as in the subject)? It show some example of connecting a dsp to a 128K memory. From the appnote, in order to make the memory mapping optimum they skip A15 and A16 from the DSP to the RAM and use A17 and A18 instead. That is done in order to allow the internal memory to be able to be addressed when OVLY bit =1. I'm currently use C5402 with a 64K memory. Currently I only skip A15(Use A16 instead). I'm thinking that by only skip A15(and use A16 and A17 instead), it should also ok for the 128K SRAM. The internal memory also should be able to access. Can someone explain why we need to skip A16 also?

TIA
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top