Understanding SSTL terminations for DDR1,2 and 3

[dk614nd]

Hi,

I need pdf or ppt or link which explains the SSTL termination used for DDR1, DDR2 and DDR3


regards

 

[cks3976]

Register on JEDEC to download the standard documents : STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18): | JEDEC

---------- Post added at 07:14 ---------- Previous post was at 06:54 ----------

Some more links :

https://www.edaboard.com/threads/130370/
SSTL Interface Description, Stub Series Terminated Logic for DDR, DDR2, DDR3 Electrical layer, SSTL-2, SSTL-18, SSTL-3
http://www.ece.unh.edu/courses/ece711/refrense_material/hs_memory/sstl_2spec.pdf : An old standard, but useful reading
http://www.ti.com/lit/an/scba014/scba014.pdf