Understanding of a program in system verilog

[maxxtorr723]

HI,
I am new to system verilog and was trying to simulate the following simple program but am not able to understand how the output is beign generated:

---

Code Verilog - [expand]
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module test ();
initial
  begin
    byte XYZ[4][7];
    foreach(XYZ[i,j])
      XYZ[i][j]=i*100+j;
    foreach (XYZ[i])
      begin
        $write("%d:",i);
        foreach(XYZ[,j])
          $write("%3d",XYZ[i][j]);
                //$display
                end
        end
endmodule

---

the result that it is generating is
0: 0 1 2 3 4 5 6 1:100101102103104105106 2:-56-55-54-53-52-51-50 3: 44 45 46 47 48 49 50


I am able to understand logic behind 0: 0 1 2 3 4 5 6 1:100101102103104105106 but how 2:-56-55-54-53-52-51-50 3: 44 45 46 47 48 49 50 is coming could someone please explain??

 

[dave_59]

Because byte is an 8-bit signed integer, and you are assigning it a 32-bit expression i*100+j. The result will overflow and get truncated.