Understanding DDR3 DRAM configuration

[shaiko]

Hello,

I'm trying to learn about the various configuration options of DDR3 memory.
For example, please review the following document:

**broken link removed**

At Page 11, Table 2, Row 2 - you see this:
1Gb / (8M × 16 × 8) × 2 SDRAMs

This is how I understand it:

1Gb - Is the total capacity of the DRAM chip.

8M - Is the size of every memory sub-array. It is organized internally into rows and columns (CAS/RAS) when every row/column intersection addresses only a single bit per sub-array.

16 - Is the width of the input/output data of the chip. A single bit comes from every memory sub-array and concatenated to the total width. Therefore, the width exactly matches the number of memory sub-arrays per bank.

8 - Is the number of banks per dram chip.

Is my observation correct?

 

[ads-ee]

Is my observation correct?

Looks okay to me, nothing else would make sense for the table.

 

[shaiko]

How are different banks accessed on the same DRAM chip?
Does every bank have a different offset row address?

 

[ads-ee]

I haven't done much work with DDR3. Perhaps this might help you out.

 

[shaiko]

Thanks for your help.
This is one of the (many) documents I've stumbled upon before posting.
It has good information about timing, but doesn't discuss memory configuration in detail.

 

[malli_1729]

Physical banks were accessed using BA0,1,2 signals.