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Unconstrained FPGA ADC-Outputs

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Hugo17

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Hello
I do have a ADC connected to an FPGA while the FPGA generates the ADC-Clock. This ADC-clock is the same as used insided the FPGA.
After running TimeQuest I see that for example the ADC_Clock and the ADC_OE outputs are unconstrained output ports of the FPGA.

Questions: :-|
- How do I constrain those two outputs (ADC_Clock / ADC_OE) correctly? Can I 'simply' use the 'set_output_delay?
- Do I need to know the delay inside the FPGA to the output pin and if yes, how can I determine such delay?
- Or can I set a false path to the ADC_Clock for example because at the end it only matters when the ADC-Data are coming in to the FPGA?

Thanks.!
 

For slow and medium fast IO, I would consider
Code:
set_false_path -to [all_outputs]
set_false_path -from [all_inputs]
 

ok understood. In this case I use a clock of 125MHz.
If we consider this as fast IO, how would you determine the delay time(s) respectively how to constrain the IO's in such case?
 

Hi,

125MHz is 8ns.
4ns HIGH and 4ns low.

I would initially set my input/output delay values between 1 - 3 ns. Then if the placer fails (most probably it will) timing I will look at the timing analysis report and then determine the exact delay values needed. FPGA routing will highly dictate these delay values.
 
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