uncertainty setting during synthesis

Status
Not open for further replies.
S

sun_ray

Advanced Member level 3
Joined
Oct 3, 2011
Messages
772
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,298
Activity points
6,828
What are the all reasons behind setting the set_clock_uncertainty with respect to a virtual clock and not with respect the real clock while doing RTL synthesis?
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…