Unassociated port error during elaboration of design

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ashishk

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Hi,

I am using vcs for simulations.RTL is in VHDL. During elaboration phase I am getting one error "Error-[ANL-UNASSO-PORT] Illegal port association , Unassociated port <port_name> of mode IN in entity <entity_name> has no default value. Can anyone tell me what does this mean?

Thanks,
Ashish
 

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