Unable to run C/RTL cosimulation in Vivado HLS

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sai_shashi

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Hi there,
I have the matrix multiplication example code from xilinx which i am trying to implement on the FPGA. I defined the interfaces and performed c-simulation and synthesis. But to proceed, the C/RTL cosimulation field is inactive. Ho do i resolve this? what is the possible cause?

Thanks in advance
 

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