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ultimate frequency for adder in Design ware library

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they

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Does anybody face the problem when sythesis can't met the timing (around 400Mhz to 500Mhz) constraint when adder in Synopsys Design Ware library is used in a module, with some multiplexers added in the design? The technology used is 0.13um... and synthesized with Design Compiler...
 

eda_wiz

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500MHz (2ns) is very less time for an adder even in .13u... try instantiating DW CSA adder.

BTW u should use DW foundation library and not DW basic.
 

they

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whizkid said:
they said:
Does anybody face the problem when sythesis can't met the timing (around 400Mhz to 500Mhz) constraint when adder in Synopsys Design Ware library is used in a module, with some multiplexers added in the design? The technology used is 0.13um... and synthesized with Design Compiler...
500MHz (2ns) is very less time for an adder even in .13u... try instantiating DW CSA adder.

BTW u should use DW foundation library and not DW basic.
Hi, thanks for your reply : )

The DW library i am using is the basic one as I don't have the license for foundation version. So do you think it is possible to run the synthesis for adder mention above (with some multiplexer added to the design) under frequency of 500Mhz with DW basic? Anyway, my synthesis failed, just want to make sure nothing wrong.
 

eda_wiz

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DW basic only have ripple carry and CLA adders.
Even if u dont have DW foundation lic u can synthesise with DW foundation and see the results for evaluation purposes. Issue is u cant write out the netlist. I think 500 Mhz speed is too much and wonder for which application u need that much speed. Otherwise u can instantiate gates from the technology library directly.
 

they

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whizkid said:
DW basic only have ripple carry and CLA adders.
Even if u dont have DW foundation lic u can synthesise with DW foundation and see the results for evaluation purposes. Issue is u cant write out the netlist. I think 500 Mhz speed is too much and wonder for which application u need that much speed. Otherwise u can instantiate gates from the technology library directly.

rgds
whizkid
Hi, once again thanks for your reply....
As I am still new to the IC Design field, just trying with different frequency for synthesis... You mean 500Mhz is very high for normal application? (Sorry for the stupid question, as i am not very sure about the frequency used for normal application, except for PC processor which is a common knowledge)
 

they

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whizkid said:
DW basic only have ripple carry and CLA adders.
Even if u dont have DW foundation lic u can synthesise with DW foundation and see the results for evaluation purposes. Issue is u cant write out the netlist. I think 500 Mhz speed is too much and wonder for which application u need that much speed. Otherwise u can instantiate gates from the technology library directly.

rgds
whizkid
Hi, for using cla, i just use "set_implementation cla ADDSUB", but after I replace cla with csa, error occurs that shows DC can't find library implementation of csa.... May I know how to solve the problem?
BTW...... actually i was using DW addsub instead of DW add. So does csa implementation exist in DW addsub?
 

don_quixote

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First you didn't mention what is your bit length. Some adder structure can vary a lot in timing with respect to bit width. Second multiplexers from standard cell library may kind of slow, pass transistor logic is popular for this purpose. Finally, 500M actually is not that high for 0.13 technology. If you still couldn't meet the timing, try to look at the critical path to see what is the problem
 

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