udp in verilog...help me plzzzzzzz............

[harsh49]

help me for this program...its not functioning as it should be as per program.....

primitive tflip(q,t,clk,reset);

output q;
reg q;
input t,clk,reset;
initial

q=1'b0;

table
//t clk reset q q+
? ? 1 :?:0;
? ? (10) :?:0;
? ? (01) :?:0;
? ? (x?) :?:0;
? ? (?x) :?:0;
? (10) ? :?:1;
0 (01) 0 :?:0;
1 (01) 0 :0:1;
1 (01) 0 :1:0;
endtable
endprimitive

 

[ljxpjpjljx]

please explain clearly which problem you meet?

 

[harsh49]

at negetive edge of the clk.....this program is working as a the togling condition...which should not be work like it ...since i have specified that the output should be 0 at negetive edge of clk so why it is working like a positive edge of clk.....