Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 entity spi_loopback is Generic ( N : positive := 32; -- 32bit serial word length is default CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase. PREFETCH : positive := 2; -- prefetch lookahead cycles SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK ); Port( ----------------MASTER----------------------- m_clk_i : IN std_logic; m_rst_i : IN std_logic; m_spi_ssel_o : OUT std_logic; m_spi_sck_o : OUT std_logic; m_spi_mosi_o : OUT std_logic; m_spi_miso_i : IN std_logic; m_di_req_o : OUT std_logic; m_di_i : IN std_logic_vector(N-1 downto 0); m_wren_i : IN std_logic; m_do_valid_o : OUT std_logic; m_do_o : OUT std_logic_vector(N-1 downto 0); ----- debug ----- m_do_transfer_o : OUT std_logic; m_wren_o : OUT std_logic; m_wren_ack_o : OUT std_logic; m_rx_bit_reg_o : OUT std_logic; m_state_dbg_o : OUT std_logic_vector(3 downto 0); m_core_clk_o : OUT std_logic; m_core_n_clk_o : OUT std_logic; m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0); ----------------SLAVE----------------------- s_clk_i : IN std_logic; s_spi_ssel_i : IN std_logic; s_spi_sck_i : IN std_logic; s_spi_mosi_i : IN std_logic; s_spi_miso_o : OUT std_logic; s_di_req_o : OUT std_logic; -- preload lookahead data request line s_di_i : IN std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i) s_wren_i : IN std_logic := 'X'; -- user data write enable s_do_valid_o : OUT std_logic; -- do_o data valid strobe, valid during one clk_i rising edge. s_do_o : OUT std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i) ----- debug ----- s_do_transfer_o : OUT std_logic; -- debug: internal transfer driver s_wren_o : OUT std_logic; s_wren_ack_o : OUT std_logic; s_rx_bit_reg_o : OUT std_logic; s_state_dbg_o : OUT std_logic_vector (3 downto 0) -- debug: internal state register -- s_sh_reg_dbg_o : OUT std_logic_vector (N-1 downto 0) -- debug: internal shift register ); end spi_loopback;
You have to read the related documentations - could be from Digilent or Xilinx.so can u help in the ucf for master and slave..?
There are GPIO LEDs available on ur dev board. When complete data has been tx from the master you can make a signal go high, bring it out as a port and this can be made to drive a LED in your master board (you need to map the port to the GPIO LED in the UCF file). Similarly when complete data has been Rx by the slave, a LED can be turned on.how do i know that the data send from master and recived in slave?
but im facing problem with ucf file i set the pmod connector for master and slave"ssel,sck,mosi,miso"
Then search for the documentation that explains how an UCF file works and read it.yes sir i have the nexys3 master ucf.. but i dont how the ucf file works..
It is difficult for anyone to say with this amount of information what has gone wrong. The problem may lie anywhere beginning from the RTL code to the bit-stream downloading process.i set the clk to clk and rst to downbutton and "miso mosi sclk ss" and when i tried to send data from laptop the fpga nothing happen.
NET "m_spi_2x_clk_i" TNM_NET = m_spi_2x_clk_i;
TIMESPEC TS_m_spi_2x_clk_i = PERIOD "m_spi_2x_clk_i" 15 ns HIGH 50%;
NET "s_clk_i" TNM_NET = s_clk_i;
TIMESPEC TS_s_clk_i = PERIOD "s_clk_i" 8 ns HIGH 50%;
#Created by Constraints Editor (xc6slx45t-csg484-3) - 2011/06/08
NET "m_clk_i" TNM_NET = m_clk_i;
TIMESPEC TS_m_clk_i = PERIOD "m_clk_i" 8 ns HIGH 50%;
NET "s_spi_sck_i" TNM_NET = s_spi_sck_i;
TIMESPEC TS_s_spi_sck_i = PERIOD "s_spi_sck_i" 30 ns HIGH 50%;
NET "m_spi_sck_o_OBUF" TNM_NET = m_spi_sck_o_OBUF;
TIMESPEC TS_m_spi_sck_o_OBUF = PERIOD "m_spi_sck_o_OBUF" 30 ns HIGH 50%;
NET "Inst_spi_master/core_n_clk" TNM_NET = Inst_spi_master/core_n_clk;
TIMESPEC TS_Inst_spi_master_core_n_clk = PERIOD "Inst_spi_master/core_n_clk" 30 ns HIGH 50%;
INST "m_di_i<0>" TNM = m_di;
INST "m_di_i<1>" TNM = m_di;
INST "m_di_i<2>" TNM = m_di;
INST "m_di_i<3>" TNM = m_di;
INST "m_di_i<4>" TNM = m_di;
INST "m_di_i<5>" TNM = m_di;
INST "m_di_i<6>" TNM = m_di;
INST "m_di_i<7>" TNM = m_di;
INST "m_di_i<8>" TNM = m_di;
INST "m_di_i<9>" TNM = m_di;
INST "m_di_i<10>" TNM = m_di;
INST "m_di_i<11>" TNM = m_di;
INST "m_di_i<12>" TNM = m_di;
INST "m_di_i<13>" TNM = m_di;
INST "m_di_i<14>" TNM = m_di;
INST "m_di_i<15>" TNM = m_di;
INST "m_di_i<16>" TNM = m_di;
INST "m_di_i<17>" TNM = m_di;
INST "m_di_i<18>" TNM = m_di;
INST "m_di_i<19>" TNM = m_di;
INST "m_di_i<20>" TNM = m_di;
INST "m_di_i<21>" TNM = m_di;
INST "m_di_i<22>" TNM = m_di;
INST "m_di_i<23>" TNM = m_di;
INST "m_di_i<24>" TNM = m_di;
INST "m_di_i<25>" TNM = m_di;
INST "m_di_i<26>" TNM = m_di;
INST "m_di_i<27>" TNM = m_di;
INST "m_di_i<28>" TNM = m_di;
INST "m_di_i<29>" TNM = m_di;
INST "m_di_i<30>" TNM = m_di;
INST "m_di_i<31>" TNM = m_di;
TIMEGRP "m_di" OFFSET = IN 8 ns VALID 8 ns BEFORE "m_clk_i" RISING;
INST "m_spi_miso_i" TNM = m_miso;
INST "s_di_i<0>" TNM = s_di;
INST "s_di_i<1>" TNM = s_di;
INST "s_di_i<2>" TNM = s_di;
INST "s_di_i<3>" TNM = s_di;
INST "s_di_i<4>" TNM = s_di;
INST "s_di_i<5>" TNM = s_di;
INST "s_di_i<6>" TNM = s_di;
INST "s_di_i<7>" TNM = s_di;
INST "s_di_i<8>" TNM = s_di;
INST "s_di_i<9>" TNM = s_di;
INST "s_di_i<10>" TNM = s_di;
INST "s_di_i<11>" TNM = s_di;
INST "s_di_i<12>" TNM = s_di;
INST "s_di_i<13>" TNM = s_di;
INST "s_di_i<14>" TNM = s_di;
INST "s_di_i<15>" TNM = s_di;
INST "s_di_i<16>" TNM = s_di;
INST "s_di_i<17>" TNM = s_di;
INST "s_di_i<18>" TNM = s_di;
INST "s_di_i<19>" TNM = s_di;
INST "s_di_i<20>" TNM = s_di;
INST "s_di_i<21>" TNM = s_di;
INST "s_di_i<22>" TNM = s_di;
INST "s_di_i<23>" TNM = s_di;
INST "s_di_i<24>" TNM = s_di;
INST "s_di_i<25>" TNM = s_di;
INST "s_di_i<26>" TNM = s_di;
INST "s_di_i<27>" TNM = s_di;
INST "s_di_i<28>" TNM = s_di;
INST "s_di_i<29>" TNM = s_di;
INST "s_di_i<30>" TNM = s_di;
INST "s_di_i<31>" TNM = s_di;
TIMEGRP "s_di" OFFSET = IN 8 ns VALID 8 ns BEFORE "s_clk_i" RISING;
INST "s_spi_mosi_i" TNM = s_mosi;
INST "m_do_o<0>" TNM = m_do;
INST "m_do_o<1>" TNM = m_do;
INST "m_do_o<2>" TNM = m_do;
INST "m_do_o<3>" TNM = m_do;
INST "m_do_o<4>" TNM = m_do;
INST "m_do_o<5>" TNM = m_do;
INST "m_do_o<6>" TNM = m_do;
INST "m_do_o<7>" TNM = m_do;
INST "m_do_o<8>" TNM = m_do;
INST "m_do_o<9>" TNM = m_do;
INST "m_do_o<10>" TNM = m_do;
INST "m_do_o<11>" TNM = m_do;
INST "m_do_o<12>" TNM = m_do;
INST "m_do_o<13>" TNM = m_do;
INST "m_do_o<14>" TNM = m_do;
INST "m_do_o<15>" TNM = m_do;
INST "m_do_o<16>" TNM = m_do;
INST "m_do_o<17>" TNM = m_do;
INST "m_do_o<18>" TNM = m_do;
INST "m_do_o<19>" TNM = m_do;
INST "m_do_o<20>" TNM = m_do;
INST "m_do_o<21>" TNM = m_do;
INST "m_do_o<22>" TNM = m_do;
INST "m_do_o<23>" TNM = m_do;
INST "m_do_o<24>" TNM = m_do;
INST "m_do_o<25>" TNM = m_do;
INST "m_do_o<26>" TNM = m_do;
INST "m_do_o<27>" TNM = m_do;
INST "m_do_o<28>" TNM = m_do;
INST "m_do_o<29>" TNM = m_do;
INST "m_do_o<30>" TNM = m_do;
INST "m_do_o<31>" TNM = m_do;
#Created by Constraints Editor (xc6slx45t-csg484-3) - 2011/06/09
INST "m_rx_bit_reg_o" TNM = m_rx_bit;
## 12 pin connectors
##JB
Net "m_spi_sck_o" LOC = K2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38P_M3DQ2, Sch name = JB1
Net "m_spi_ssel_o" LOC = K1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38N_M3DQ3, Sch name = JB2
Net "m_spi_mosi_o" LOC = L4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39P_M3LDQS, Sch name = JB3
Net "m_spi_miso_i" LOC = L3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39N_M3LDQSN, Sch name = JB4
#Net "JB<4>" LOC = J3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P_M3DQ6, Sch name = JB7
#Net "JB<5>" LOC = J1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N_M3DQ7, Sch name = JB8
#Net "JB<6>" LOC = K3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N_GCLK24_M3LDM, Sch name = JB9
#Net "JB<7>" LOC = K5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = JB10
##JC
Net "s_spi_sclk_i" LOC = H3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44N_GCLK20_M3A6, Sch name = JC1
Net "s_spi_ssel_i" LOC = L7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45P_M3A3, Sch name = JC2
Net "s_spi_mosi_i" LOC = K6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45N_M3ODT, Sch name = JC3
Net "s_spi_miso_o" LOC = G3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46P_M3CLK, Sch name = JC4
#Net "JC<4>" LOC = G1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46N_M3CLKN, Sch name = JC7
#Net "JC<5>" LOC = J7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P_M3A0, Sch name = JC8
#Net "JC<6>" LOC = J6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N_M3A1, Sch name = JC9
#Net "JC<7>" LOC = F2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48P_M3BA0, Sch name = JC10
i tested in 2 fpga board with 1 uart cable from pc to master and one uart cable from slave to pc .. i used the hyperterminal to send the data along them nothing happened
not a problem in and of itself, still doesn't address the quality of the question.im not professional im just biggner in fpga and vhdl at all but what to do this is the life..
this has already been addressed above in post #1, 3, & 8, so you aren't giving any new information.the project is to send world "like hello" from hyperterminl using uart
cable hello to spi master .. the spi master receive and send it by pmod
connector to spi slave.. the spi slave receive and send it back to pc
using uart cable..
this was also mentioned by you in a previous post. Yes the interface between the two cards must be included in the UCF as the pin definitions and the timing must be set in the UCF for those pins. But also the pins for the UART connections need to be in the UCF as they connect to something external to the FPGA device.what i got tell now that the ports must be in ucf are"mosi miso ssel sck'' becuz those ports will do the transfer from master to slave fpga..
Same statement as previously, says nothing.i got nothing when send the data by the hyperterminal to fpga master..
The above statement doesn't qualify as an excuse (if that is the intention). What we want to point out is that you have not provided clear information about your problem. Also you have provided information in "bursts". This makes things difficult for members who want to help.im not professional im just biggner in fpga and vhdl at all but what to do this is the life
What!? You don't know which pins do what? Is that the problem? Then you should read a tutorial on SPI.yea good idea, but which port are responsible for sending the data back to pc from master?! which port are responsible to send the data through 3 spi wires through slave fpga ?? which port are responisble to send the data from slave to pc ???
if i knw the answers for these 3 ques i can finish the project
Obviously you should go through and understand the code or at least how to use the code (if it's properly documented IP). That's part of how you use IP. If the SPI code you have is overly complicated then it's either designed for a specific purpose with extra "features" or just plan rubbish (see my previous post about student projects posted on the internet).and if u have anycodes wirte in vhdl for spi can give it to me ? becuz i think the code that i have is complicated ..
thanks alot
SPI usually has 4 wires, SCK, MOSI, MISO, and SS (optional if you have only 1 slave, but I'd still make sure it's there and used).
Based on your description you want to connect everything in a uni-directional fashion like so.
PC_UART1_TX => FPGA1_UART_RX => FPGA1_MASTER_SPI => PMOD_SCK_MOSI_SS (MISO unused) => FPGA2_SLAVE_SPI => FPGA2_UART_TX => PC_UART2_RX
The connections used should be apparent by the names of everything.
just i want someone who can help me where to put the ports in ucf to makes the transfer done from two fpga and pc
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