UART warning messages

[pfaisalbe]

Hi

I am using SPARTAN 3 . I have done UART design. Post route simulation gives warning message as


Simulator:29 - at 205.128 ns: Warning: Timing violation in
/TESTFIXTURE4/uut/Modcount_reg_1/ $setuphold<setup>( SRST:204.756 ns,
CLK:205.128 ns,990.000 ps,0 ns)
WARNING:Simulator:29 - at 205.128 ns: Warning: Timing violation in
/TESTFIXTURE4/uut/Modcount_reg_0/ $setuphold<setup>( SRST:204.756 ns,
CLK:205.128 ns,990.000 ps,0 ns)
WARNING:Simulator:29 - at 205.128 ns: Warning: Timing violation in
/TESTFIXTURE4/uut/Modcount_reg_2/ $setuphold<setup>( SRST:204.756 ns,
CLK:205.128 ns,990.000 ps,0 ns)
WARNING:Simulator:29 - at 205.128 ns: Warning: Timing violation in
/TESTFIXTURE4/uut/Modcount_reg_3/ $setuphold<setup>( SRST:204.756 ns,
CLK:205.128 ns,990.000 ps,0 ns)
WARNING:Simulator:29 - at 209.128 ns: Warning: Timing violation in
/TESTFIXTURE4/uut/Modcount_reg_1/ $setuphold<setup>( SRST:208.593 ns,
CLK:209.128 ns,990.000 ps,0 ns)
WARNING:Simulator:29 - at 209.128 ns: Warning: Timing violation in
/TESTFIXTURE4/uut/Modcount_reg_0/ $setuphold<setup>( SRST:208.593 ns,
CLK:209.128 ns,990.000 ps,0 ns)





I have used period constraint. What should be done to get rid of this message or Can I ignore this warning message ?

Regards

Faisal

 

[atulaxc]

Is SRST asynchronous reset in your design? If so then false path all paths involving *srst.

**broken link removed**

 

[mrflibble]

Well, the warning mean precisely what it says. You are violating the setup time of those flipflops.

If you don't know why that is, chances are this is going to be a problem in real hardware. This was post PAR you say? What does the timing report say after place & route? No violations?

During simulation the register that have the setup violation will be set to X. Usually this is what you want, since you want to know that the value is unknown due to possible metastability.

If you really really want to then you can set the offending registers to async.

(* ASYNC_REG="TRUE" *) reg my_flipflop_used_in_asynchronous_logic;

This will prevent the simulator from assigning X's to timing violated registers. So that way you can simulate asynchronous logic. But usually that is NOT what you want.

So if this is a low speed uart, then probably this is due to something being async. Like atulaxc already asked.... I would also guess that SRST is async, given the above messages. If SRST is async it might be a good idea to use a reset synchronizer, so that you have asynchronous reset assertion and synchronous de-assertion.