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UART start and stop bits : Confusion

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pawan kumar

Member level 4
Jan 31, 2012
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Hi Friends,

I got this doubt when I had to capture the UART transmission through an oscilloscope as an assignment. My Understanding :

I have setup a baud rate of 9600bps with 1 start bit, 1 stop bit, no pairity bit and 8 data bits.
In this entire discussion, I refer to the Voltage levels and polarity of a Microcontroller (5V).
So, a single frame consists of 10 bits. On measuring, I get a data bit to be 104us wide.(Not sure about this).

My understanding is that Start bit is a High to low transition, lasting for a time interval which is more than the time of a single bit. Likewise, a stop bit is a low to high transition.

Every frame starts with a start bit and ends with a stop.

Now my question is :
1)What is the exact duration of start/stop bit? (What does it mean when they say 1 start bit and show its width exactly the same as data bits in a few tutorials)

2)Consider a case where D0.......D7 is this : 10001001 (0x91). here, how does the computer not get fooled on sensing the 1000? ( I am unable to distinguish this sequence with the start bit).

As soon as I am clear, I would like to post a nice diagram which would be helpful for other beginners like me.


Start bit has same duration as other bits. But it's sampled by the UART 1/2 bit duration after the falling edge, and the subsequent bits after 1 bit duration each.

Bit position in the UART frame is only unequivocal after a new start bit. If you lose synchronicity, you have to wait for an idle peridod of at least a frame length.
Okay, So, suppose I plug out and re-connect the cables half way through and it finds a High to low transition. If the bit length is the same for start bit and the normal low, How does it deduce the start bit without an error?

Quite simple, any falling edge out of UART receiver idle state is considered a frame start.

- then check for valid start bit after 1/2 bit duration,
- read in 8 data bits
- check for valid stop bit

either signal data received or frame error
Thanks FvM,
This makes sense to me.

Moreover, I feel that every Falling edge would be monitored for a possible start bit in parallel until a Valid start bit has been recognized.

Correct me if am wrong.


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