UART/RS232 using Verilog and Spartan-3E starter kit

[MPTSheff]

I'm trying to activate various LED patterns on the Spartan 3E starter kit by sending a signal from the connected PC. I've implemented the example from https://www.fpga4fun.com/SerialInterface.html along with a constraints file I wrote from the information in the user guide (below).

# ==== Clock Source ====
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33;
NET "clk" PERIOD = 5ns HIGH 40%;
# ==== Discrete GPout (LED) ====
NET "GPout<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GPout<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GPout<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GPout<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GPout<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GPout<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GPout<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GPout<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
# ==== DTE ====
NET "RxD" LOC = "U8" | IOSTANDARD = LVTTL ;
NET "TxD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;

Using Hyperterminal I can activate various LEDs through keystrokes, and sending data-files of 0s and 1s also activates the LED. It appears that only the last number in the file produces any result eg. transferring a file containing 01111111 produces the same output as entering "1" in the hyperterminal.

Clearly, I do not understand what output I should expect (I had assumed the output would be the LEDs displaying my transferred bit-pattern). I wondered whether the other bits in the file were being accessed/displayed too quickly for me to perceive? Are there any further tutorials/examples I might build upon?

My desired result is that a file containing a series of patterns like the earlier example, be processed by the FPGA displaying each pattern in turn. Presumably I would also need to include some kind of delay to stop this occurring to rapidly.

 

[mrflibble]

I think this may be an expectation error. Type: ABCDEFGHIJK ... etc and see the 8-bit count on the LED display increment by 1 with each key stroke...

 

[MPTSheff]

Thank you for such a quick reply. Yes, you are indeed correct. It works exactly as you had said.

However, I still pose the question regarding file transfer. Transferring a file of "ABCDEFGH" then shows the same display as typing "H". Was my guess that the transfer is simply too quick to perceive the display correct? In which case I presume I would need to slow down the baud rate in order to see the change in real time?

 

[TrickyDicky]

I doubt slowing the baud rate would make a perceptable difference. You need to delay the sending of the individual characters.

 

[MPTSheff]

Ah, hang on, I think I spot another misunderstanding on my part. The baud rate determines the speed of data transfer from the PC to the FPGA, whereas I assumed it was to the LED (ie. the entire project).

In which case, if I introduce a state machine, say, a 24 bit counter, and only output after a complete cycle, that should provide the delay I require. Presumably there will also be some issue regarding the storing of my data between the FPGA receiving the data from the PC and the signal being outputted to the LED display?

 

[TrickyDicky]

yes, you'd need some storage, but a FIFO should be easy enough to insert.

 

[mrflibble]

Ah, hang on, I think I spot another misunderstanding on my part.

As said, expectation error. But sounds like you are now adjusting your expectations to coincide with reality, so problem solved real soon. As you notice, your design only remembers the last character sent. If you need more characters stored you could use a shift register or a fifo as TrickyDicky suggested.