[SOLVED] uart ip :: how to tranfer a register value from fpga to c code

hi
i need to use uart ip from quartus (using qusy) , i got a reference program with soc kit.

https://www.youtube.com/watch?v=7xJ9dhVDCwU

here my intention is i:: there is a design running in my fpga @ (200 hz & 46 bit width) . output is coming out from top module in 46 bit register. i wanted to print or save it in my pc. after few searching, i thought i will do usb _uart( which i had in my fpga) .

is it possible to change the c code using in the video so that instead of "" hello world"" , am i able to print/ save my register value ?

i am able to do it, how can i transfer value from my verilog module to c code for printing ? saving ??

any help is really appreciated & thanks in advance


regards

dipin said:

is it possible to change the c code using in the video so that instead of "" hello world"" , am i able to print/ save my register value ?

Click to expand...

yes, make the register accessible via the Avalon bus and add that to the Nios II system design, or you can use whatever QSYS uses as GPIO and connect the GPIO to your register.

i am able to do it, how can i transfer value from my verilog module to c code for printing ? saving ??

Click to expand...

By reading the the aforementioned register that is now memory mapped in the Nios II address space on the Avalon bus and writing to whatever the address of the usb_uart is.

hi,
thanks for the replay ads-ee, cleared my doubt now. so i am thinking to use it through avalon bus so that i can control it from pc (future work)

so i need to add my "top module" & "external bus to avalon bridge ip" along with (nios II processor +onchip ram+UART(rs_232 serial port)) in qsys system right?

first time i am doing something like this . thats why i am asking all these doubts. i am really sorry if these doubts are silly

regards

dipin said:

hi,
thanks for the replay ads-ee, cleared my doubt now. so i am thinking to use it through avalon bus so that i can control it from pc (future work)

so i need to add my "top module" & "external bus to avalon bridge ip" along with (nios II processor +onchip ram+UART(rs_232 serial port)) in qsys system right?

Click to expand...

Yes that is what you will do...though admittedly easier said than done. ;-)

My advice find one of the Qsys tutorials that are on Altera's website and go through that at least for the first attempt to understand the flow.

hi,

input OSC_50_B8A;


//////////// HSMC, HSMC connect to ADA - High Speed ADC/DAC //////////
output ADC_CLK_A;
output ADC_CLK_B;
input [13:0] ADC_DA;
input [13:0] ADC_DB;
output ADC_OEB_A;
output ADC_OEB_B;
input ADC_OTR_A;
input ADC_OTR_B;

input reset;
output out_clk1;
output out_clk2;
output [7:0] x_out;
output [7:0] y_out;

Click to expand...

above one is my top module declaration..( in qsys system i am adding only my top module)
so i just need x_out, and y_out to print on my pc, when i declare the custom component in my qsys system can i able to delete all other signals and only include x_out, y_out and clk and reset ????

if not possible then i need to do multiple avalon slaves right?
is it necessory to add external bus to avalon bridge ip as same number of times as avalon slaves?

regards