UART interface FPGA - uC

[flote21]

Hi guys!

I am trying to interface a FPGA and PIC18FL4520 through an UART. Both chips has the same power supply: 3v3 and there is a direct connection between the FPGA and uc using 2 pcb tracks.

Is it necessary to place a level translataor or some kind of pull up resistor in these lines (TX and RX)? As I told previously, I don't have anything and by default the uC and the FPGA is driving to high level both lines. Then when the communication starts, the pulses are generated, but at the endof the comunication, one of the line (RX_in input to the FPGA) is driving to low level by the FPGA while th uC is driving to high level. It is like the FPGA pin is hang up...But the it is srtange because this interface has been used in other boards with the same FPGA and uC and exactly the same pin connections (2 direct tracks btwen chips) and it was working always...

Any suggestion?

Thanks.

 

[FvM]

It's a 3-wire interface (Rx, Tx, Gnd) and doesn't need level converters.

It's mysterious how the FPGA Rx line (an input port) should drive low. But as everything is programmed in your FPGA configuration, only you can know what's happening. If you want help, post relevant information.

 

[KlausST]

Hi,

(RX_in input to the FPGA) is driving to low level by the FPGA

an input should never drive LOW

I don´t expect problems. On each line there is exactely one output and one input.

No need for a pullup, or a resistor. No need for level translators.

Check:
* maybe there is a short circuit on the PCB
* or a short circuit on the IC pins/pads
* if the pins are configured correctely (not only in the source files, but also in the output files)
* if traces are short and not influenced by other (switched, power) signals. How long?
* Tx of one IC goes to Rx of the other IC. Check crossing.

Klaus

 

[flote21]

Hi guys I have already solve the problem. One of the I/O pin of the FPGA is broken and it was giving 3v3, only 1v. This pins was responsible to reset the uC and for this reason, the uC was always reset tied to low level the Tx FPGA pin...my question now is: How is it possible that one of the I/O pin is broken. Normally the complete I/O bank is broken right?

I think that maybe I did somthing wrong in the scheme. Please find attached the scheme and tell me if there is some error in the MCLR pin of the uC. As you can see this pin is controlled by the FPGA and the JTAG uc programmer. I am afraid about the short circuit marked in the scheme in pink. Maybe this is the reason because the FPGA I/O pin is broken....Any idea?

 

[KlausST]

Hi,

regarding MCLR:
* uC is not the problem, because it is an input.
* RC is not the problem, becuase it is high impedance
--> problematic could be when JTAG and FPGA drive different levels at the same time.

you could use a current limiting resistor in the MCLR line. Depending on what position you set the resistor you give either JTAG or FPGA the priority.


Klaus

 

[FvM]

Some points are unclear. PIC18 programming interface isn't using JTAG protocol. In case the programmer uses HV programming mode, the MCLR line must not directly connect to a FPGA pins. A series resistor and clamping diodes should be used.

 

[flote21]

It is using HV programming, you are right. So I should not connect it to the FPGa directly. Any schematic with clamp diodes to avoid this?

Thanks.

Some points are unclear. PIC18 programming interface isn't using JTAG protocol. In case the programmer uses HV programming mode, the MCLR line must not directly connect to a FPGA pins. A series resistor and clamping diodes should be used.