UART DESIGNING >>>I NEED HELP

[naaj_ila]

hai all....
i want to design uart...(i am just alone)
actually i dont know anything abt that
..
first i had read ...asynchronous data communication ...then modems and then rs 232...and i had jumped to do micro uart project..which was in this site
h**p://www.cmosexod.com/micro_uart.htm

plz help me guys ...
i may ask a lot of questions...it may be silly ..but plz help me

my ques>>>

why the incoming bits (8 bits ) and stop bit are sampled only at the 'bit cell centre'
and start bit is sensed while it has a transition from logic1 to logic0..

the figure link is given below;;;;

**broken link removed**

plz give ur suggestions also...in doing this project

i may ask further questions later...
thanxs in advance

 

[hys]

Bit Clk is much faster than the data you transmit. And in real time, there is a possibility of some unpredictable delays on the TX / RX lines... so the data might be shifted +vely or -vely by a few bit clks.... In order to counter this phenomenon it is usually a practice to sample the data at the middle..

Start bit or stop bit that you have mentioned is something that the UART protocol defines... we just have to accept it..

Best Regards,
Harish