uable to define in verilog(Model Sim)

[Kiran Sahu]

sir,
There is problem in defining macros in verilog(compiled in Model Sim)
like Here I used n in program as

module test();
`define n 8
wire i;
assign i = n;
endmodule

then it shows an error as "Undefined variable: n"
kindly, help me out of this error. As I would like to define n in the global scope so that I can use it in another program.

 

[ljxpjpjljx]

you can put define ahead of module declaration!

 

[FvM]

As I would like to define n in the global scope so that I can use it in another program.

`define is a preprocessor feature, it's not exported to other design entities respectively has no "scope". It's not clear what you exactly want to achieve, but you should think about using either module parameters or project wide include files.